Fall 2004EE 3563 Digital Systems Design EE 3563 Combinational Design Practices  Change in reading assignment: 5.3.1,  SSI – Small Scale Integration –Logic gates (AND, OR, NOR, XOR, etc.) –Very simple circuits  MSI – Medium Scale Integration –More complex circuits, encoders, decoders, etc. –20 to 200 gates  LSI – Large Scale Integration –200 to 200,000 gates  VLSI – Very Large Scale Integration –Dividing line between LSI and VLSI a little fuzzy –Over 1 million transistors

Fall 2004EE 3563 Digital Systems Design EE 3563 Drawing Rules  Some general guidelines to follow when drawing MSI and LSI devices  Will usually draw a rectangle, I.e. the package in which the circuit is housed  Show inputs on the left, outputs on the right –Sometimes may need to show power and ground, may use top/bottom of package  Show active low inputs/outputs using the bubble  Don’t NOT use a double negative –The sentence above actually says to use a double negative (DON’T) –If you do, your outputs will make as much sense –So, if you label a pin Y`, do not then show an active low output with the bubble  Term Alert!!! --- DIP --- what is a DIP?

Fall 2004EE 3563 Digital Systems Design EE 3563 Drawing Rules  Term Alert!!! --- DIP --- what is a DIP?  Dual Inline Package  The chips I passed around were DIPs!  Rectangular, with pins on two sides  There are a variety of package types  Single Inline Packages, Ball-Grid Array, surface mount, etc.

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  Combinational Programmable Logic Devices (PLD)  Originally, Programmable Logic Arrays (PLA)  PLA is a combinational two-level AND-OR device  Can be programmed to realize any S.O.P. logic expression –Limited by number of inputs, product terms, and outputs –Each product term requires an AND gate –Each AND gate has a limit on inputs Must have 2 inputs for every input of PLA --- one input is inverted –Each output requires an OR gate –OR gate has limit on number of inputs –The number of inputs for the OR gate is equal to ??????

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  A PLA is specified by inputs, outputs, and product terms  An n * m PLA with p product terms means that the PLA has n inputs, m outputs, and p product terms

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  Can we use the previous PLA to realize the function here? YZ WX

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  Write the minimal solution: –X*Z + W*Y’ + W*X + W’*X’*Y  How many inputs?  How many outputs?  How many product terms?  Yes, the previous PLA can do this logic function and two more, assuming they use some of the same product terms YZ WX

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  A more compact diagram can be used  Has the lines represented in a “bus like” manner  Can be programmed for constant zero or one outputs also  The little “X’s” are fuses that can be opened by a high voltage

Fall 2004EE 3563 Digital Systems Design EE 3563 Programmable Logic Devices  Some devices can only be programmed once  Others can be erased by applying ultraviolet light  You may have seen chips with little windows  Other devices (such as flash memory) can be programmed and reprogrammed many times electronically  Numerous technologies for these devices  The text briefly describes some of these technolgies

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  Multiple input, multiple output circuit that converts some input sequence to some output sequence  The input typically has fewer bits than the output  Typically, a decoder has a 1:1 mapping -- a particular input combination will produce a specific, unique, output  Most common type is the 1-out-of-m decoder which only asserts one of the m output pins at any time  A seven-segment decoder is a practical example  Have 10 input code words, 0 – 9, seven output code words --- this decoder is atypical!

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  The n-to-2 n decoder is the most common 1-out-of-m decoder –Called a binary decoder  The input is a binary number which asserts a single output

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  74x139 Dual 2-to-4 Decoder

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  Application – can be used to activate 1 of 4 components  A 3-to-8 decoder could activate 1 of 8 devices  In the lectures, we are building a small microprocessor computer, which could record and playback sound  As we cover components, I will apply them to our design  One use of the decoder is to select a particular set of memory chips

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders μPμP Memory 2 Memory 1 8-bit Data Bus Assume each memory is 64 kBytes 2-to-4 Decoder Memory 0 Memory 3 Enable Pin

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  74x138 3-to-8 Decoder

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders  74x138 3-to-8 Decoder

Fall 2004EE 3563 Digital Systems Design EE 3563 Decoders