The Inclusive (Measurement ) FVTX aka iFVTX sponsored by LANL-DR in FY ‘06-08 FPIX Chip Module/Hybrid Testcard Pixel Plane Assembly/Integration

The Interaction Region at Phenix Space for Vertex upgrade detectors

Outline  From Hybrid to Module  From Module to Testcard  From Testcard to Pixel Plane  From Pixel Plane to Station  From Station to Full Detector

Pixel Module FPIX2 Silicon Sensor HDI Support Structure Wire bonds NOT TO SCALE VTT

8 Chip Module Dimensions: 111.0mm x 11.1mm + 2x 10.0mm x 11.1 mm tabs Dimensions: 111.0mm x 11.1mm + 2x 10.0mm x 11.1 mm tabs Line width: 50  m Line width: 50  m Line to line clearance: 50  m Line to line clearance: 50  m Metal layer thickness: 12  m Metal layer thickness: 12  m Number of layers: 4 Number of layers: 4 Via pad/hole: 150/70  m Via pad/hole: 150/70  m Lamination: 25  m epoxy Lamination: 25  m epoxy Film thickness (polymide): 50  m Film thickness (polymide): 50  m HDI designed by Fermilab/ made by (?) Mircoconex/Dyconex /CERN: HDI CAD top layer. HDI + 8 bare die chips. HDI + 8 chips with detector. (SINTEF PSPRAY) Several iterations, now minimal HDI

Production Flow  Chip and Sensor Test  Hybridization by VTT  Hybrid Test  HDI Electrical Test  Module Assembly  Test-card Assembly  Test and Burn-in  Pixel Plane Assembly  Test and Burn-in

Pixel Module Assembly Fixture with Vaccum Chuck Gluing of FPIX to HDI

Testcard and Wire Bonding Testcard for each module Gluing of module to card Wirebonding of HDI to card

Ready Test Card

PCI-based Test stands – PTA card  Perform module test ‘PINGA’ test software Initial characterization with inject pulser Hit map Absolute calibration Burn-in (normal operation for 72 hours) Repeat hit map Q&A and module classification 

Module Removal for Plane Assembly

4 Stations in FVTX Frame  2 Planes per Station  6 Identical Planes for Stations 2,3,4  Smaller Plane for Station 1  Room Temperature

PCB The Layout of a Plane Cooling TPG FPIX on HDI Power Bias Pulser LVDS Output Voltage

The Actual Plane and Stations  Flex Blades (Temperature compensation)  Two Planes Sandwich to get Station Modules Inside Connectors Outside

Large Pixel Plane (10 modules) Active components are Repeater and Regulator Delivery Imminent

Small Pixel Plane Concept (4-5 Modules)

Module Mounting and Cooling PEEK tube HDI TPG Sensor Readout Chip Placing and wirebonding Cooling with Fluor-carbon at temperature that keeps the HDI at assembly temperature

Cables to Pole Face  Five flat cables either side of active area on plane  20 per large station, 12 per small station, total 72  48 low voltage, high voltage cables

Status and Plans  Status All FPIXs are procured All Si-detectors are procured 15 Hybrids are delivered 25 HDIs delivered, preparing production order 10 module PCBs delivered Several test cards are ready Wire bonding at Si-det Test stands are ready Assembly gigs are ready

Preproduction and Production Plan  Proto (spare) TPG TPG + Cooling Test PCB Mate PCB TPG Test 15 Modules on Cards Test Assemble Plane Test  Production TPG TPG + Cooling Test PCB 3 small - 6 large Mate PCB TPG Test 88 Modules on Cards Test Assemble Planes Test Assemble Stations Cage Assemble Detector VTT Rework ? 15 FPIX only Modules on Cards Test Assemble Plane Test

Plan Encapsulate TPG for full system 2 weeks Test cooling final system Add Cooling Tubes enpsulate PP TPG Prepare 1 10m PP for full tests Add PP Cooling Test PP Cooling the 1m SPARE Stuff 10m PP for full tests Mate TPG and 10m PP Add Fiducals for pp test Place Modules on 10m pp Etest Cooling Test Fabricate PP 10 Planes Stuff 1 planesFPIX Etes t 10 planes

iFVTX FPIX Module Station 8 chip module 4 Pixel Planes