EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011 Professor Ronald L. Carter

Slides:



Advertisements
Similar presentations
Ideal Junction Theory Assumptions Ex = 0 in the chg neutral reg. (CNR)
Advertisements

ECE 663 Ideal Diode I-V characteristic. ECE 663 Real Diode I-V characteristic.
EE 5340 Semiconductor Device Theory Lecture 18 – Spring 2011 Professor Ronald L. Carter
Semiconductor Device Modeling and Characterization – EE5342 Lecture 6 – Spring 2011 Professor Ronald L. Carter
PN Junction Diodes.
Integrated Circuit Devices
EE 5340 Semiconductor Device Theory Lecture 12 – Spring 2011 Professor Ronald L. Carter
Department of Aeronautics and Astronautics NCKU Nano and MEMS Technology LAB. 1 Chapter IV June 14, 2015June 14, 2015June 14, 2015 P-n Junction.
Lecture #25 OUTLINE BJT: Deviations from the Ideal
L14 March 31 EE5342 – Semiconductor Device Modeling and Characterization Lecture 14 - Spring 2005 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 14 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 8 - Fall 2009 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 11 – Spring 2011 Professor Ronald L. Carter
Semiconductor Device Modeling and Characterization – EE5342 Lecture 09– Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 13 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 26 - Fall 2010 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 08 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 21 – Spring 2011
L08 Feb 081 Lecture 08 Semiconductor Device Modeling and Characterization EE Spring 2001 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 15 - Fall 2009 Professor Ronald L. Carter
Empirical Observations of VBR
Semiconductor Devices Lecture 5, pn-Junction Diode
Semiconductor Device Modeling and Characterization – EE5342 Lecture 12 – Spring 2011 Professor Ronald L. Carter
L9 February 151 Semiconductor Device Modeling and Characterization EE5342, Lecture 9-Spring 2005 Professor Ronald L. Carter
L06 31Jan021 Semiconductor Device Modeling and Characterization EE5342, Lecture 6-Spring 2002 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 15 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 27 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 19 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 22 - Fall 2010
EE 5340 Semiconductor Device Theory Lecture 22 – Spring 2011 Professor Ronald L. Carter
Dr. Nasim Zafar Electronics 1 EEE 231 – BS Electrical Engineering Fall Semester – 2012 COMSATS Institute of Information Technology Virtual campus Islamabad.
EE5342 – Semiconductor Device Modeling and Characterization Lecture 10 Spring 2010 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 23 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 25 – Spring 2011 Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 10 – Fall 2010 Professor Ronald L. Carter
Semiconductor Device Modeling and Characterization – EE5342 Lecture 10– Spring 2011 Professor Ronald L. Carter
L04,... June 11,...1 Electronics I EE 2303/602 - Summer ‘01 Lectures 04,... Professor Ronald L. Carter
1 Concepts of electrons and holes in semiconductors.
L17 March 221 EE5342 – Semiconductor Device Modeling and Characterization Lecture 17 - Spring 2005 Professor Ronald L. Carter
L09 12Feb021 Semiconductor Device Modeling and Characterization EE5342, Lecture 9-Spring 2002 Professor Ronald L. Carter
Professor Ronald L. Carter
Chapter 6. pn Junction Diode
Professor Ronald L. Carter
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 16 – Spring 2011
EE 5340 Semiconductor Device Theory Lecture 13 - Fall 2010
Professor Ronald L. Carter
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 19 – Spring 2011
Professor Ronald L. Carter
Professor Ronald L. Carter
Professor Ronald L. Carter
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 18 – Spring 2011
EE 5340 Semiconductor Device Theory Lecture 12 - Fall 2009
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 26 - Fall 2009
Deviations from the Ideal I-V Behavior
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 13 - Fall 2009
Professor Ronald L. Carter
Professor Ronald L. Carter
Professor Ronald L. Carter
EE 5340 Semiconductor Device Theory Lecture 17 - Fall 2003
EE 5340 Semiconductor Device Theory Lecture 16 - Fall 2009
EE 5340 Semiconductor Device Theory Lecture 11 - Fall 2003
EE 5340 Semiconductor Device Theory Lecture 13 – Spring 2011
EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011
EE 5340 Semiconductor Device Theory Lecture 20 - Fall 2010
Professor Ronald L. Carter
Presentation transcript:

EE 5340 Semiconductor Device Theory Lecture 17 – Spring 2011 Professor Ronald L. Carter

©rlc L17-24Mar20112 Summary of V a > 0 current density eqns. Ideal diode, J s expd(V a /(  V t )) –ideality factor,  Recombination, J s,rec exp(V a /(2  V t )) –appears in parallel with ideal term High-level injection, (J s *J KF ) 1/2 exp(V a /(2  V t )) –SPICE model by modulating ideal J s term V a = V ext - J*A*R s = V ext - I diode *R s

©rlc L17-24Mar20113 V ext ln(J) data Effect of R s V KF Plot of typical V a > 0 current density equations

©rlc L17-24Mar20114 For V a < 0 carrier recombination in DR The S-R-H rate (  no =  po =  o ) is

©rlc L17-24Mar20115 Reverse bias (V a carrier gen in DR Consequently U = -n i /     = mean min. carr. g/r lifetime

©rlc L17-24Mar20116 Reverse bias (V a < 0), carr gen in DR (cont.)

©rlc L17-24Mar20117 E crit for reverse breakdown (M&K**) Taken from p. 198, M&K**

©rlc L17-24Mar20118 Reverse bias junction breakdown Avalanche breakdown –Electric field accelerates electrons to sufficient energy to initiate multiplication of impact ionization of valence bonding electrons –field dependence shown on next slide Heavily doped narrow junction will allow tunneling - see Neamen*, p. 274 –Zener breakdown

©rlc L17-24Mar20119 Reverse bias junction breakdown Assume -V a = V R >> V bi, so V bi -V a -->V R Since E max ~ 2V R /W = (2qN - V R /(  )) 1/2, and V R = BV when E max = E crit (N - is doping of lightly doped side ~ N eff ) BV =  (E crit ) 2 /(2qN - ) Remember, this is a 1-dim calculation

©rlc L17-24Mar Junction curvature effect on breakdown The field due to a sphere, R, with charge, Q is E r = Q/(4  r 2 ) for (r > R) V(R) = Q/(4  R), (V at the surface) So, for constant potential, V, the field, E r (R) = V/R (E field at surface increases for smaller spheres) Note: corners of a jctn of depth x j are like 1/8 spheres of radius ~ x j

©rlc L17-24Mar BV for reverse breakdown (M&K**) Taken from Figure 4.13, p. 198, M&K** Breakdown voltage of a one-sided, plan, silicon step junction showing the effect of junction curvature. 4,5

©rlc L17-24Mar Diode equivalent circuit (small sig) IDID VDVD VQVQ IQIQ  is the practical “ideality factor”

©rlc L17-24Mar Small-signal eq circuit C diff C depl r diff C diff and C depl are both charged by V a = V Q VaVa

©rlc L17-24Mar Diode Switching Consider the charging and discharging of a Pn diode –(N a > N d ) –W n << Lp –For t < 0, apply the Thevenin pair V F and R F, so that in steady state I F = (V F - V a )/R F, V F >> V a, so current source –For t > 0, apply V R and R R I R = (V R + V a )/R R, V R >> V a, so current source

©rlc L17-24Mar Diode switching (cont.) + + VFVF VRVR D R RFRF Sw R: t > 0 F: t < 0 V F,V R >> V a

©rlc L17-24Mar Diode charge for t < 0 xnxn x nc x pnpn p no

©rlc L17-24Mar Diode charge for t >>> 0 (long times) xnxn x nc x pnpn p no

©rlc L17-24Mar Equation summary

©rlc L17-24Mar Snapshot for t barely > 0 xnxn x nc x pnpn p no Total charge removed, Q dis =I R t

©rlc L17-24Mar I(t) for diode switching IDID t IFIF -I R tsts t s +t rr I R

©rlc L17-24Mar201121

©rlc L17-24Mar201122

©rlc L17-24Mar Ideal diode equation for E gN = E gN J s = J s,p + J s,n = hole curr + ele curr J s,p = qn i 2 D p coth(W n /L p )/(N d L p ), [cath.] = qn i 2 D p /(N d W n ), W n > L p, “long” J s,n = qn i 2 D n coth(W p /L n )/(N a L n ), [anode] = qn i 2 D n /(N a W p ), W p > L n, “long” J s,n >N d, W n & W p cnr wdth

©rlc L17-24Mar Ideal diode equation for heterojunction J s = J s,p + J s,n = hole curr + ele curr J s,p = qn iN 2 D p /[N d L p tanh(W N /L p )], [cath.] = qn iN 2 D p /[N d W N ], W N > L p, “long” J s,n = qn iP 2 D n /[N a L n tanh(W P /L n )], [anode] = qn iP 2 D n /(N a W p ), W p > L n, “long” J s,p /J s,n ~ n iN 2 /n iP 2 ~ exp[[E gP -E gN ]/kT]

©rlc L17-24Mar Bipolar junction transistor (BJT) The BJT is a “Si sandwich” Pn  (P=p +,  =p - ) or Np  (N=n +, =n - ) BJT action: npn Forward Active when V BE > 0 and V BC < 0 P n  EBC V EB V CB Charge neutral Region Depletion Region

©rlc L17-24Mar npn BJT topology Charge Neutral Region Depletion Region x x’ p-Base -CollectorN-Emitter z 0 WBWB W B +W C -W E 0 x” c x” 0 xBxB 0 x’ E IEIE ICIC IBIB

©rlc L17-24Mar BJT boundary and injection cond (npn)

©rlc L17-24Mar BJT boundary and injection cond (npn)

©rlc L17-24Mar IC npn BJT (* Fig 9.2a)

©rlc L17-24Mar References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986.

©rlc L17-24Mar References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986.