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EE 5340 Semiconductor Device Theory Lecture 17 - Fall 2003

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Presentation on theme: "EE 5340 Semiconductor Device Theory Lecture 17 - Fall 2003"— Presentation transcript:

1 EE 5340 Semiconductor Device Theory Lecture 17 - Fall 2003
Professor Ronald L. Carter L 17 Oct 21

2 Summary of Va > 0 current density eqns.
Ideal diode, Jsexpd(Va/(hVt)) ideality factor, h Recombination, Js,recexp(Va/(2hVt)) appears in parallel with ideal term High-level injection, (Js*JKF)1/2exp(Va/(2hVt)) SPICE model by modulating ideal Js term Va = Vext - J*A*Rs = Vext - Idiode*Rs L 17 Oct 21

3 Plot of typical Va > 0 current density equations
ln(J) data Effect of Rs Vext VKF L 17 Oct 21

4 For Va < 0 carrier recombination in DR
The S-R-H rate (tno = tpo = to) is L 17 Oct 21

5 Reverse bias (Va<0) => carrier gen in DR
Consequently U = -ni/2t0 t0 = mean min. carr. g/r lifetime L 17 Oct 21

6 Reverse bias (Va< 0), carr gen in DR (cont.)
L 17 Oct 21

7 Ecrit for reverse breakdown (M&K**)
Taken from p. 198, M&K** L 17 Oct 21

8 Reverse bias junction breakdown
Avalanche breakdown Electric field accelerates electrons to sufficient energy to initiate multiplication of impact ionization of valence bonding electrons field dependence shown on next slide Heavily doped narrow junction will allow tunneling - see Neamen*, p. 274 Zener breakdown L 17 Oct 21

9 Reverse bias junction breakdown
Assume -Va = VR >> Vbi, so Vbi-Va-->VR Since Emax~ 2VR/W = (2qN-VR/(e))1/2, and VR = BV when Emax = Ecrit (N- is doping of lightly doped side ~ Neff) BV = e (Ecrit )2/(2qN-) Remember, this is a 1-dim calculation L 17 Oct 21

10 Junction curvature effect on breakdown
The field due to a sphere, R, with charge, Q is Er = Q/(4per2) for (r > R) V(R) = Q/(4peR), (V at the surface) So, for constant potential, V, the field, Er(R) = V/R (E field at surface increases for smaller spheres) Note: corners of a jctn of depth xj are like 1/8 spheres of radius ~ xj L 17 Oct 21

11 BV for reverse breakdown (M&K**)
Taken from Figure 4.13, p. 198, M&K** Breakdown voltage of a one-sided, plan, silicon step junction showing the effect of junction curvature.4,5 L 17 Oct 21

12 Diode equivalent circuit (small sig)
ID h is the practical “ideality factor” IQ VD VQ L 17 Oct 21

13 Small-signal eq circuit
Cdiff and Cdepl are both charged by Va = VQ Va Cdiff rdiff Cdepl L 17 Oct 21

14 Diode Switching Consider the charging and discharging of a Pn diode
(Na > Nd) Wn << Lp For t < 0, apply the Thevenin pair VF and RF, so that in steady state IF = (VF - Va)/RF, VF >> Va , so current source For t > 0, apply VR and RR IR = (VR + Va)/RR, VR >> Va, so current source L 17 Oct 21

15 Diode switching (cont.)
VF,VR >> Va F: t < 0 Sw RF R: t > 0 VF + RR D + VR L 17 Oct 21

16 Diode charge for t < 0 pn pno x xn xnc L 17 Oct 21

17 Diode charge for t >>> 0 (long times)
pn pno x xn xnc L 17 Oct 21

18 Equation summary L 17 Oct 21

19 Snapshot for t barely > 0
pn Total charge removed, Qdis=IRt pno x xn xnc L 17 Oct 21

20 I(t) for diode switching
ID IF ts ts+trr t - 0.1 IR -IR L 17 Oct 21

21 L 17 Oct 21

22 L 17 Oct 21

23 Ideal diode equation for EgN = EgN
Js = Js,p + Js,n = hole curr + ele curr Js,p = qni2Dp coth(Wn/Lp)/(NdLp), [cath.] = qni2Dp/(NdWn), Wn << Lp, “short” = qni2Dp/(NdLp), Wn >> Lp, “long” Js,n = qni2Dn coth(Wp/Ln)/(NaLn), [anode] = qni2Dn/(NaWp), Wp << Ln, “short” = qni2Dn/(NaLn), Wp >> Ln, “long” Js,n<<Js,p when Na>>Nd , Wn & Wp cnr wdth L 17 Oct 21

24 Ideal diode equation for heterojunction
Js = Js,p + Js,n = hole curr + ele curr Js,p = qniN2Dp/[NdLptanh(WN/Lp)], [cath.] = qniN2Dp/[NdWN], WN << Lp, “short” = qniN2Dp/(NdLp), WN >> Lp, “long” Js,n = qniP2Dn/[NaLntanh(WP/Ln)], [anode] = qniP2Dn/(NaWp), Wp << Ln, “short” = qniP2Dn/(NaLn), Wp >> Ln, “long” Js,p/Js,n ~ niN2/niP2 ~ exp[[EgP-EgN]/kT] L 17 Oct 21

25 Bipolar junction transistor (BJT)
The BJT is a “Si sandwich” Pnp (P=p+,p=p-) or Npn (N=n+, n=n-) BJT action: npn Forward Active when VBE > 0 and VBC < 0 P n p E B C VEB VCB Charge neutral Region Depletion Region L 17 Oct 21

26 npn BJT topology x x’ p-Base n-Collector N-Emitter z WB WB+WC -WE x”c
Charge Neutral Region Depletion Region x x’ p-Base n-Collector N-Emitter z WB WB+WC -WE x”c x” xB x’E IE IC IB L 17 Oct 21

27 BJT boundary and injection cond (npn)
L 17 Oct 21

28 BJT boundary and injection cond (npn)
L 17 Oct 21

29 IC npn BJT (*Fig 9.2a) L 17 Oct 21

30 References * Semiconductor Physics and Devices, 2nd ed., by Neamen, Irwin, Boston, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Muller and Kamins, John Wiley, New York, 1986. L 17 Oct 21


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