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EE 5340 Semiconductor Device Theory Lecture 26 - Fall 2010 Professor Ronald L. Carter

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Presentation on theme: "EE 5340 Semiconductor Device Theory Lecture 26 - Fall 2010 Professor Ronald L. Carter"— Presentation transcript:

1 EE 5340 Semiconductor Device Theory Lecture 26 - Fall 2010 Professor Ronald L. Carter ronc@uta.edu http://www.uta.edu/ronc

2 Table 8.4 (p. 398 M&K 3 rd edition) Charge Conditions in the MOS System L26 24Nov20102

3 Figure 8.11 (p. 399 M&K 3 rd edition) General behavior of C-V curves of an ideal MOS system under different dc bias and ac small-signal conditions. The low-frequency (LF) C-V curve corresponding to the simplified model is shown as a dashed line. L26 24Nov20103

4 Figure 8.12 (p. 401 M&K 3 rd edition) MOS C-V measurement system. The voltmeter and ammeter measure both the magnitude and phase of the voltage across the diode and the current through it. L26 24Nov20104

5 Figure 8.14a & b (p. 404 M&K 3 rd edition) The effects of a fixed oxide-charge density Q ox on the MOS system. (a) Charge configuration at zero bias: Q ox = Q s + Q G ; (b) charge at flat band: Q ox = Q G. L26 24Nov20105

6 Figure 8.15 (p. 405 M&K 3 rd edition) Fixed charge in the oxide causes the capacitance-voltage curve to translate along the V G axis without distortion (dashed curve); charge that is influenced by the gate voltage causes distortion (dotted curve). L26 24Nov20106

7 Figure 8.16 (p. 406 M&K 3 rd edition) (a) Four categories of oxide charge in the MOS system. The symbols for the charge densities Q (C cm -2 ), and state densities N (states cm -2 ) or D (states cm - 2 eV -1 ) have been standardized [4]. (b) Energy levels at the oxide-silicon interface. The interface trapping levels are distributed with density D it (states cm -2 eV -1 ) within the forbidden-gap energies. L26 24Nov20107

8 8 Effect of Q’ ss on the C-V relationship Fig 10.29*

9 L26 24Nov20109 Fully biased n-MOS capacitor 0 y L VGVG V sub =V B E Ox,x > 0 Acceptors Depl Reg e - e - e - e - e - e - n+ VSVS VDVD p-substrate Channel if V G > V T

10 L26 24Nov201010 MOS energy bands at Si surface for n-channel Fig 8.10**

11 L26 24Nov201011 n-substrate inversion (p-channel) Fig 10.7*

12 L26 24Nov201012 Computing the D.R. W and Q at O.S.I. ExEx E max x

13 L26 24Nov201013 Q’ d,max and x d,max for biased MOS capacitor Fig 8.11** x d,max (  m)

14 L26 24Nov201014 Fully biased n- channel V T calc

15 L26 24Nov201015 n-channel V T for V C = V B = 0 Fig 10.20*

16 L26 24Nov201016 Fully biased p- channel V T calc

17 L26 24Nov201017 p-channel V T for V C = V B = 0 Fig 10.21*

18 L26 24Nov201018 Equations for V T calculation

19 L26 24Nov201019 n-channel enhancement MOSFET in ohmic region 0< V T < V G V B < 0 E Ox,x > 0 Acceptors Depl Reg V S = 0 0< V D < V DS,sat e - e - e - e - e - n+ p-substrate Channel

20 L26 24Nov201020 Conductance of inverted channel Q’ n = - C’ Ox (V GC -V T ) n’ s = C’ Ox (V GC -V T )/q, (# inv elect/cm 2 ) The conductivity  n = (n’ s /t) q  n G =  n (Wt/L) = n’ s q  n (W/L) = 1/R, so I = V/R = dV/dR, dR = dL/(n’ s q  n W)

21 L26 24Nov201021 Basic I-V relation for MOS channel

22 L26 24Nov201022 I-V relation for n-MOS (ohmic reg) IDID V DS V DS,sat I D,sat ohmic non-physical saturated

23 L26 24Nov201023 Universal drain characteristic 9I D1 IDID 4I D1 I D1 V GS =V T +1V V GS =V T +2V V GS =V T +3V V DS saturated, V DS >V GS -V T ohmic

24 L26 24Nov201024 Characterizing the n-ch MOSFET VDVD IDID D S G B V GS VTVT

25 L26 24Nov201025 Substrate bias effect on V T (body-effect)

26 L26 24Nov201026 Body effect data Fig 9.9**

27 L26 24Nov201027 Low field ohmic characteristics

28 L26 24Nov201028 MOSFET circuit parameters

29 L26 24Nov201029 MOSFET circuit parameters (cont)

30 L26 24Nov201030 Fig 10.51* MOSFET equivalent circuit elements

31 L26 24Nov201031 MOS small-signal equivalent circuit Fig 10.52*

32 L26 24Nov201032 MOS channel- length modulation Fig 11.5*

33 L26 24Nov201033 Analysis of channel length modulation

34 L26 24Nov201034 Channel length mod- ulated drain char Fig 11.6*

35 L26 24Nov201035 References * Semiconductor Physics & Devices, by Donald A. Neamen, Irwin, Chicago, 1997. **Device Electronics for Integrated Circuits, 2nd ed., by Richard S. Muller and Theodore I. Kamins, John Wiley and Sons, New York, 1986


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