RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes 3-4 Sept. 2008EFW INST+SOC PDR217 RBSP Electric Field and Waves Instrument (EFW) Instrument Data Processing Unit (IDPU) Preliminary Design Review Michael Ludlam Space Sciences Laboratory UC Berkeley

Sept. 2008EFW INST+SOC PDR EFW – IDPU –Introduction –Requirements –Block Diagram –Board Overview –Specifications –Heritage –Spacecraft & Inter-board Interfaces –Backplane –Shielding –Resources –I&T –Schedule –Personnel

Sept. 2008EFW INST+SOC PDR IDPU Introduction –Scope of Presentation Gives overview of Instrument Data Processing Unit (IDPU). Areas that are handled at the IDPU top level are discussed in detail here. Individual board details, requirements and designs are discussed during those board presentations. –Synopsis: IDPU houses most of the instrument electronics, providing the electrical interface between the spacecraft and the sensor / boom units. It contains four circuit boards: Low Voltage Power Supply (LVPS) and Power Control Board Circuit (PCB) Digital Control Board (DCB) Digital Fields Board (DFB) Boom Electronics Board (BEB)

Sept. 2008EFW INST+SOC PDR IDPU Requirements Requirements for IDPU are derived from the EFW System Requirements (RBSP_EFW_SYS_001_Requirements) Only requirements that are directly relevant to the IDPU as a unit are reported here. Individual board level requirements are detailed in appropriate presentations.

Sept. 2008EFW INST+SOC PDR IDPU Block Diagram

Sept. 2008EFW INST+SOC PDR IDPU Board Overview –IDPU Contains 4 Boards: LVPS & PCB (SSL) – Power supply and switching. Receives power from S/C and converts it to board required voltages. Converters all synchronized together at one frequency. Boom deployment voltages are S/C provided but switched on the PCB circuit. DCB (SSL) – Processor Board, Memory and S/C Digital Interface. Accepts and responds to incoming S/C commands and sends Housekeeping and compressed Science Data in Telemetry stream. On card memory stores data received from DFB. DFB (LASP) – Analog and Digital Signal Processing. Processes signals from sensors and digitizes them to produce waveform and spectral products that are sent to the DCB board. BEB (SSL) – Boom Sensor Control. Supplies bias current and control voltages to set the sensors to the correct operating regime.

Sept. 2008EFW INST+SOC PDR IDPU Electrical Specifications –Board Specification Documents: RBSP_EFW_LVPS_001E_Specification RBSP_EFW_DCB_003C_Specification RBSP_EFW_DFB_001A_SPECrev2_04_25_08 RBSP_EFW_BEB_001B_Specification RBSP_EFW_BPL_001G_Specification

Sept. 2008EFW INST+SOC PDR IDPU Heritage –RBSP IDPU is heavily based on the successful THEMIS IDPU, failure free in orbit combined operation for over 7 years. THEMIS IDPU itself was based on a long history of instrumentation at SSL/UCB. THEMIS IDPU

Sept. 2008EFW INST+SOC PDR IDPU External Electrical Interfaces IDPU provides interface to S/C via: –1 x 15M DSub Connector on the LVPS (Instrument and Boom Deploy Power). –1 x 9F DSub Connector on the DCB (Instrument Commands, 1PPS/SP, Instrument Telemetry). –Interfaces are defined in the APL Controlled EFW ICD ( ) – currently RevB. –low level signals have been verified by APL provided GSE. IDPU provides interface to boom units via: –3 x 26F HDSub Connectors on the BEB board (Defined in BEB Specification – RBSP_EFW_BEB_001). –1 x 62F HDSub Connector on the LVPS/PCB board (Defined in LVPS/PCB Specification – RBSP_EFW_LVPS_001). –Verified during instrument I&T. IDPU provides interface to EMFISIS via: –pins on 3 x 26F HDSub Connectors on BEB Board (EFW out). –1 x 26M HDSub Connector on DFB (FGM, SCM in). –Interfaces are defined in the APL Controlled EFW to EMFISIS ICD ( ) – currently RevD. –Verified by EFW – EMFISIS interface test.

Sept. 2008EFW INST+SOC PDR IDPU Internal Electrical Interfaces –IDPU Boards plug into a backplane board that provides board to board connections – power, command, telemetry, and housekeeping. –Digital board to board interfaces are: DCB – DFB : UCB ‘CDI’ interface – serial data protocol for command and telemetry using a common clock. DCB – BEB : Controls DACs via command, clock and latch lines, muxes with bi level control signals, test signal (AC Test) – 2 lines. DCB – PCB : Command, Clock and Strobe line control decoders on PCB circuit. THEMIS Backplane – note different number of connectors. THEMIS IDPU Backplane

Sept. 2008EFW INST+SOC PDR IDPU Backplane –IDPU Backplane schematics are complete. –Layout is waiting on final board spacing inside the IDPU box. Once this is finalized the board can go to layout. –All pins are connected, or tied to ground (no floating pins). –Card uses two types of connector (DIN96, Hypertronics 80pin) both flown on THEMIS. –Initial board to board tests use a GSE backplane that is mounted in a standard VME 19” rack.

Sept. 2008EFW INST+SOC PDR IDPU Telemetry Flow diagram DFBSDRAM FLASH FSW S/C I/F 80kbs S/C 8.38Mbs Configuration Commands 512 Packet Headers/s >10Mb/s >10Mbs 256 Packets/s Flowchart shows the capability of telemetry flow from DFB to S/C. System is able to handle maximum data rate from DFB. Limiting factor is interface to S/C. 8.38Mbs Ground Commands HK, Spin Fits, Diagnostics

Sept. 2008EFW INST+SOC PDR Shielding Provision is made for EMC/EMI board shields on the LVPS, DCB and DFB. No radiation spot shielding is anticipated on any IDPU board – radiation shielding is done at box level (covered by IDPU Mechanical Design presentation). LVPS Shield DCB Shield DFB Shield BEB Board

Sept. 2008EFW INST+SOC PDR IDPU Power All power for EFW is routed through the IDPU, including that to deploy booms. The supplies for the IDPU (PCB, DCB and DFB) and the BEB are independent that allows the BEB to function in the event of failure on another IDPU board and still provide EMFISIS with boom sensor signals. Average Power

Sept. 2008EFW INST+SOC PDR Mass Resources IDPU Mass is 8.29kg (CBE) and has a NTE of 10.37kg (25%) IDPU board mass estimates are based on THEMIS equivalent boards and appropriately updated (extra circuitry on DCB, BEB etc). CBE Mass

Sept. 2008EFW INST+SOC PDR Subsystem Testing IDPU I&T Flow: –Individual IDPU boards delivered to IDPU for integration once they have met board requirements. –Board to board interfaces are then verified. –Integration will follow written test procedure. –Unit is assembled in box and functionally tested (e.g. CPT). –IDPU then ready for IDPU level FSW testing, IDPU to SPB/AXB testing or IDPU environmental tests. –Further I&T descriptions are dealt in I&T presentation.

Sept. 2008EFW INST+SOC PDR Personnel LVPS & PCB : Peter Berg (SSL) DCB : Michael Ludlam & Dorothy Gordon (SSL) FSW : Peter Harvey (SSL) DFB : Wesley Cole, Ken Stevens, Susan Batiste (LASP) BEB : Jane Hoberman (SSL) IDPU : Michael Ludlam, Rachel Hochman (SSL) CHASSIS : William Donakowski (SSL) GSE : William Rachelson (SSL) PARTS: Ron Jackson & Jorg Fischer (SSL)

Sept. 2008EFW INST+SOC PDR Schedule IDPU Schedule is kept up to date and reported monthly. Key Dates: LVPS ETU Ready: 12/22/08 DCB ETU Ready: 12/29/08 DFB ETU Delivered to UCB: 1/21/09 BEB ETU Ready: 1/5/09 ETU IDPU delivery to I&T: Feb 09 F1 IDPU delivery to I&T: Oct 09 F2 IDPU delivery to I&T: Nov 09

RBSP Radiation Belt Storm Probes RBSP Radiation Belt Storm Probes 3-4 Sept. 2008EFW INST+SOC PDR235 RBSP Electric Field and Waves Instrument (EFW) Data Control Board (DCB) Preliminary Design Review Michael Ludlam Space Sciences Laboratory UC Berkeley

Sept. 2008EFW INST+SOC PDR Data Control Board –Introduction –Requirements –Block Diagram –Specification –Board Overview –Design –Interfaces –Heritage –Resources –Breadboard –ETU –Parts –Schedule RBSP DCB Breadboard

Sept. 2008EFW INST+SOC PDR DCB Introduction –Scope of Presentation Gives overview of DCB board. DCB FPGA Actel presentation follows and is only presented as a component in this presentation. EFW FSW is detailed in a separate presentation. –Synopsis: The DCB card; provides the digital interface between the S/C and the rest of the instrument. receives, packetizes and stores science data before transmitting it to the spacecraft. receives and transmits housekeeping to the spacecraft. receives and acts on commands from the spacecraft.

Sept. 2008EFW INST+SOC PDR Requirements DCB only requirements are listed. FSW requirements are covered in FSW presentation.

Sept. 2008EFW INST+SOC PDR EFW Block Diagram

Sept. 2008EFW INST+SOC PDR Board Overview Actel FPGA contains CAST IP Z80 core. Processor clocked at MHz (2 24 Hz). Software is stored in PROM (32kB) and EEPROM (128kB) and transferred to SRAM (128kB) on boot. Data is stored in SDRAM (256MB) and FLASH (32GB) that are on private buses. Commands are received on the S/C interface and acted on by the FSW. Inter-board communication is controlled by the DCB, using a slightly different interface for each board (detailed in IDPU presentation). Data is received on two lines from the DFB and stored directly to SDRAM using DMA channels in the FPGA. Burst data is transferred to and from the FLASH memory from SDRAM. Housekeeping is received on the backplane and on board and multiplexed into a single ADC. Telemetry (Science Data and Housekeeping) is sent to the S/C using LVDS interface. Circuit fits on single 6U card (233mm x 160mm)

Sept. 2008EFW INST+SOC PDR DCB Block Diagram

Sept. 2008EFW INST+SOC PDR DCB Specifications –DCB Board Specification Document: RBSP_EFW_DCB_003C_Specification –DCB FPGA Specification Document: RBSP_EFW_DCB_001F –FSW Specification Document: RBSP_EFW_FSW_003_Specification

Sept. 2008EFW INST+SOC PDR Interfaces –DCB has digital interface to S/C via 9F DSub Connector (Instrument Commands, 1PPS/SP, Instrument Telemetry). –Interface is defined in the APL Controlled EFW ICD ( ) – currently RevB. –Signal levels have been verified by APL provided GSE. –DCB also has an external 51-way connector to help during I&T. Connector cover will be installed on delivery of IDPU to APL. –Internal IDPU communications are routed on the 96pin DIN connector that connects to the backplane.

Sept. 2008EFW INST+SOC PDR Heritage –Heritage DCB is based on THEMIS equivalent board (also called the DCB). Much of the FPGA logic is the same (converted from schematics to VHDL). Although processor is different (RBSP: Z80, THEMIS: 8085) instruction set is compatible and allows reuse of FSW modules. SDRAM is identical to one flown on THEMIS. SRAM, EEPROM are 3.3V equivalent parts of those flown on THEMIS. ADC & Mux are identical to ones flown on THEMIS. Regulator (3.3V & 1.5V) is based on design used on THEMIS. –New IP Core – prototyped on breadboard. Flash – prototyped on breadboard. LVDS – tested on breadboard, APL recommended parts.

Sept. 2008EFW INST+SOC PDR Resources –Mass CBE 469g, NTE 586g (Includes 25% margin). –Power CBE 1.18W, NTE 1.48W (Includes 25% margin).

Sept. 2008EFW INST+SOC PDR Breadboard DCB During Phase B and breadboard circuit was built up to test new developments: IP Core inside FPGA and Flash memory. Board will also act as good test environment while engineering unit is being built up over next few months. Flash Based FPGA External Z80 (so far not needed) PROM EEPROM SRAM SDRAM FLASH Memory S/C Interface ADC

Sept. 2008EFW INST+SOC PDR Breadboard Testing Results Processor has worked extremely successfully in FPGA. Good support from vendor. Very useful to be able to simulate processor in FPGA simulation program (ModelSim). Flash memory cannot be cold spared. SDRAM, PROM, EEPROM and SRAM have been successfully tested. ADC successfully tested. S/C Interface tested Method to download code to breadboard has worked well. Breadboard testing of regulator and Flash/SDRAM switches is being tested on a separate board.

Sept. 2008EFW INST+SOC PDR DCB ETU Schematics are nearly complete for the ETU, recent changes are being implemented. Layout will start as soon as schematics are complete. ETU will use engineering versions of all the flight parts. Initial prototyping of the FPGA will be done with a reprogrammable flash FPGA (same as breadboard) on a socket. Initially, PROM will be replaced with EEPROM.

Sept. 2008EFW INST+SOC PDR DCB ETU Layout Proposed major component placements

Sept. 2008EFW INST+SOC PDR IC Parts List & Status FPGA – Part is being procured by APL for UCB. Space Qualified Actel. PROM / EEPROM / SRAM – All parts meet TID / SEE Immune (up to 80 MeVcm 2 /mg) SDRAM – Flown on THEMIS. Approved for use by APL. Rad Tolerant and SEE Immune (up to 80 MeVcm 2 /mg). FLASH – Meets TID and APL happy with SEU data, APL approved waiver with proposed use strategy to deal with SEFI performance. ADC – Meets TID, APL approved waiver for SEU. LVDS – APL recommended part used.

Sept. 2008EFW INST+SOC PDR Schedule DCB progress is tracked in the IDPU Schedule. TaskCompletion Date ETU Schematics9/5/08 ETU Layout9/26/08 Board Fabrication10/10/08 Board Assembly10/24/08 Test11/21/08 Board to IDPU Dates:ETU 12/29/08 F1 7/31/09 F2 8/14/09

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