JEITA – DASC Joint Meeting January 29, 2010 Yokohama, Japan

DASC Overview Stan Krolikoski January 29, 2010

Agenda 1. Call to Order 2. Introductions 3. JEITA standardization activities update by Kojima and Yamamoto-san 4. DASC activities update by Stan 5. Topics 1. P1666-System C by Imai-san and Stan 2. P1481-SSPEF by Kanamoto-san 6. AOB

DASC Officers Stan Krolikoski, Cadence, Chair Karen Bartleson, Synopsys, Vice Chair Kathy Werner, Freescale, Secretary Victor Berman, self, Treasurer

DASC Standards Issued in (OCI) 1481 (OLA) 1685 (IP-XACT) 1800 (SystemVerilog) 1801 (UPF) SDF is currently in a “reaffirmation Ballot”

IEEE P1076.1VHDL-AMS WG Charter: Revise, maintain and enhance IEEE Std : IEEE Standard VHDL Analog and Mixed-Signal Extensions Adds support for continuous time and mixed-signal modeling to VHDL First approved in 1999 Maintenance revision approved in 2007 IEEE Std : IEEE Standard VHDL Analog and Mixed-Signal Extensions— Packages for Multiple Energy Domain Support Definitions for electrical, thermal, mechanical, etc. energy domains First approved in 2004 Working Group activities in 2009 Developed PAR for revision of IEEE Std Maintenance revision, no new features planned Started planning for next revision of IEEE Std Incorporate IEEE Std changes into IEEE Std Enhance language by adding selected new features Planned Working Group activities for 2010 Complete revision of IEEE Std Revision of IEEE Std User survey and call for participation (January/February) Complete preliminary planning, develop PAR (March, April) Work on projects identified to be included in the revision (rest of year) Schedule depends on number of participants Contacts: Web site: WG Chair: Ernst Christen,

IEEE1647 e WG. e Functional verification language standard Currently working towards a 2010 update to the standard Donations received in 2009, now reviewing donations for inclusion. Aiming to complete review process by mid-year. Chair contact: Darren Galpin Group

IEEE P1666 SystemC WG Charter is to update the standard and to add TLM to SystemC standard Goal is to Create/ballot draft P standard in summer 2010 Send the approved standard to RevCom by end of 2010 PAR was recommended for approval by NesCom on January 22 Vote by Standards Board to end on February 4 Current discussions with IEEE to bring John Aynsley on board as technical advisor IEEE stands as intermediate between John and OSCI News Flash– contracts very closed to be signed Chair: Stan Krolikoski

IEEE 1685 IP-XACT WG Group charter Standardize the IP-XACT work done by The SPIRIT Consortium through the IEEE process 2009 milestones Documents prepared for ballot (July) Initial ballot passed with comments (August) Comments address and recirculation ballot passed (September) Package submitted to RevCom and added to December’s agenda for approval (October) RevCom approval (December) 2010 goals Publishing review in progress (January) Standard published (February) Work group’s activities are complete, currently no further work planned Contacts Chairman – Secretary –

P1699 – Rosetta WG Rosetta: The goal of Rosetta project is to provide language support for true system-level design. The Rosetta view of system level design is centers on the need to bring together information from multiple domains to predict the system-level impacts of local design decisions. In support of this, Rosetta provides mechanisms for defining system-level functional requirements and constraints, defining heterogeneous specifications and specification domains, and composing specifications to define complete systems. Individual specifications are written using semantics and vocabulary appropriate for their domains and composed to define systems. Information from multiple specification domains is composed by defining interactions between them. Charter: Develop a standard for the Rosetta System-Level Specification Language Develop a collection of Rosetta Base Domains for System-Level Specification Broaden the use of System-Level Specification in Electronics Design 2009 Milestones and Activities: Developed a semantics for Transaction Level Specification for state-based systems Developed a semantics for inter-facet synchronization and sequencing Developed initial syntax and semantics for interactions Processed over 500 issues in the standard development database Established an LRM Working Group to manage updates to the standard document Delivered tutorials at ASE and FDL 2010 Plans and Tasks: Update draft LRM to reflect additions and changes from 2009 Release the first full draft LRM for discussion in the full Working Group Finalize semantics for facets and interactions For more information: Dr. Perry Alexander, Chair – / Rosetta Web Page – System-Level Design with Rosetta, Morgan Kaufmann Publishers LRM Working Group meets weekly on Friday afternoons

P1734 – Quality IP WG Charter Provide unified quality measurement views Facilitate IP use and integration Facilitate IP improvements Based on VSIA QIP using XML Allows platform portability Facilitates user specific extensions 2009 Accomplishments Completed schema development Developed database for QIP information “Golden” XML extracted from db Completed XML validated against schema Example application developed Validates XML and schema Validates use cases 2010 Plans Complete documentation Release for ballot Re-invigorate participation Engage IP vendors and users for validation Chair

P Recommended Practice for Encryption and [Use Rights] Management of Electronic Design Intellectual Property (IP) Chartered to reconcile the IP Encryption and Design Protection technologies across the family of DASC sponsored standards through a "Recommended Practices" document, targeted at three communities: IP producers looking for best practices guidance EDA tool providers/users looking for inter-operability Working Groups looking for subject matter experts In 2009 the working group resolved inter-operability issues in IEEE Std1800 and IEEE Std1076. In 2010, the working group expects to address: License management improvements Key Management Rights Management extensions LRM specification improvements Contact: Steven J. Dovich (P1735

P1800- SystemVerilog WG Charter: To maintain and extend SystemVerilog as a Hardware Design and Verification Language In 2009, IEEE was approved and released as an official standard Including a merge of IEEE 1364 Verilog into SystemVerilog Enhancements for Assertions In 2010, approval of a new PAR and initial steps in implementation For further information contact

P1801- Design and Verification of Low Power Integrated Circuits Scope: The specification of a format to be used in defining the low power design intent for electronic systems and electronic intellectual property. The format provides the ability to specify the supply network, switches, isolation, retention and other aspects relevant to power management of an electronic system. The standard defines the relationship between the low power design specification and the logic design specification captured via other formats (e.g., standard hardware description languages). The standard provides portability of low power design specifications that can be used with a variety of commercial products throughout an electronic system design, analysis, verification and implementation flow. Activities At the end of 2008 the working group finished the final draft, which was balloted and approved in January of It was released as an IEEE Standard in March. ( The working group resumed meeting with the goal of providing answers to frequently asked questions, interpretations based on the “Sense of the Workgroup” (to be posted at and to form the scope of the next versionhttp:// Next version: After collecting *much* user feedback (see contact) Currently projected: Contact: (Gary Delp, Silver Loon

Backup

P1666 Officers Stan Krolikoski (OSCI DR) Chair-elect Jerome Cornet (ST DR) Vice Chair- elect Dennis Brophy (Mentor DR) Secretary

P1666 Member Entities Accellera Cadence Freescale Intel JEITA Mentor NXP OSCI ST Micro STARC Synopsys TI