1. IEEE Standards for Design Automation: Their Impact on the Semiconductor Industry Karen Bartleson Sr. Director, Community Marketing, Synopsys, Inc. Vice Chair, IEEE-SA Design Automation Standards Committee Member, IEEE-SA Corporate Advisory Group Global Standards at IEEE 9 March 2010

2. Agenda What is Electronic Design Automation? –IC Design Flow –EDA Standards Under IEEE Benefits of EDA Standards –to EDA Tool Developers –to EDA Users EDA Standards Collaboration with Industry Case Studies in EDA Standards

3. EDA: Where Electronics Begins Software “tools” for chip design –Architecture design –Functional design and verification –Physical design and verification –Various electrical analyses Standards improve productivity –Tool interoperability –Data exchange, sharing, and consistency

4. Let’s Make a Lot of Money! Semiconductor chips are pervasive Semiconductor industry is about $256.3B* EDA industry is about $4.6B* –Annual revenue:  Synopsys 1.37B*  Cadence 863M*  Mentor 830M*  Magma 128M* –Market share*: S – 30%, M – 18%, C – 19% Market drivers include: –Time-to-market –Global competition –Lower costs –Technology: smaller, faster, denser * 2009 Productivity increases 10X every 6 years!

5. Source: Wikipedia http://en.wikipedia.org/wiki/File:SoCDesignFlow.svg A Generic Design Flow …

6. Synopsys Example Design Flow Technology TechnologyProcess Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Gate-levelnetlist Testbench Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Specification Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Scripts Initial constraints SystemAnalysis System Studio SaberSelectArchitecture Module Compiler Models / IP Library Compiler DesignWare IP VERA RTL Verification VCS-MX ATPG TetraMAX Synthesis Design Compiler Power Compiler DFT Compiler Gate-levelverification VCS-MX Magellan Formality PrimeTime Place & Route IC Compiler Physical Compiler Links-to-Layout Design Planning PrimeTime NanoSim HSPICE Post-RouteVerification Physical Data Creation Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back Blah blah blah yada Blah blah blah yidie yadie So on and so forth on and on Jibber jabber jibber just jawing Yackety yack Ya'll com back GDSII JupiterXT Proteus Physical Design Checks STAR- RCXT Hercules RTL Gates DesignConstraints Mask Writer CATS

7. EDA Standards Under IEEE IEEE Std #Description 1076VHDL 1149JTAG (Test) 1364Verilog HDL 1450Standard Test Interface Language (STIL) 1481Delay & Power Calculation System (DPCS) 1497Standard Delay Format (SDF) 1647Functional Verification Language ‘e’ 1666System C LRM 1685IP-XACT 1735IP Encryption and Rights Management 1800System Verilog 1801Unified Power Format (UPF) 1850Property Specification Language (PSL)

8. Don’t have to address entire design flow –Too complex for small EDA companies Focus on core strengths –Standards help partition the problem Integrate tools in design team’s flow –Interoperability means new business opportunities Ability to promote own technology for widespread usage as a standard Benefits to EDA Tool Developers

9. Benefits to EDA Tool Users Portability of design data across multiple tools Users’ in-house special-purpose tools integrate easily with commercial tools Reuse of design data –Among different projects –Among different design teams Faster learning curve Build customized design flow to suit specific requirements Better management over tool purchases

10. EDA Standards Collaboration with Industry Availability of the standard is synchronized with many marketing/promotional activities –Several product rollouts –Launching of web site  (e.g., www.systemverilog.org) –Consultants doing tutorials –Seminar series by vendors –User groups –Papers, articles, blogs, … Wide adoption by user community –When the standard solves REAL problems, it is quickly adopted –Marketing the standard helps to accelerate its adoption rate –Wider community adoption accelerates tool maturity, use models, and entirely new methodologies –Leads to continued enhancement of the standard

11. EDA Standards Collaboration with Industry (cont.) EDA standards-setting organizations bridge to IEEE –Accellera, SPIRIT, OSCI/SystemC –Incubate standards, then transfer to IEEE EDA’s IEEE standards are sponsored by –Design Automation Standards Committee (DASC) –Test Technology Council (TTC)

12. Case Study: SystemVerilog – A Success from Concept to Standard Computer language for IC design An industry-wide collaborative effort that started in 2001 –Co-Design, Inc. “invented” Superlog, a derivative/enhancement of Verilog HDL (IEEE 1364) –Company acquired by Synopsys in 2001 –Superlog, with many other internal technologies, proposed as extensions to Verilog for system-level modeling, design, and verification –Called “SystemVerilog”, created by Accellera –Six technology donations and many enhancements –New entity-based IEEE WG (P1800) formed after Accellera approved its SystemVerilog standard

13. SystemVerilog Journey Ratified as IEEE Std. 1800-2005 –Started with SystemVerilog 3.1a from Accellera –Less than one year from transfer to ratification –More than 200 products support the standard –Rapid adoption across design and verification community Ratified as IEEE Std. 1800-2009 –Verilog IEEE 1364 completely integrated –Large user community looking for design and verification productivity improvement Free tutorial on IEEE Standards Education website

14. SystemVerilog Spawned an Entirely New Business Segment Enabled/accelerated IP (design blocks) market segment –One language to write complex design blocks –Same language to verify design blocks –Make IP once, sell many times Many IP providers for design and verification reuse –Networking, wireless, and consumer applications Verification IPs as much in demand as design IPs –New methodologies invented  Assertion based verification, testbench automation –Clear inflection point in the industry to deal with large System-on-Chips

15. Case Study: UPF – A Low-Power IC Standard Ever-growing need for low-power ICs in mobile/portable devices and data centers Industry recognized need for low-power IC standard –Common way for design and verification engineers to describe IC’s low-power properties EDA users and vendors came together to develop a format and methodology –Effort started in 2006 under Accellera –Merged 6 technology donations for multi-faceted requirements –Unified Power Format (UPF) created in 6 months Ratified as IEEE Std. 1801-2009 –Less than 18 months under entity process

16. Conclusions EDA users and vendors have embraced IEEE standards for three decades Large user community active in development of standards along with vendors Standards help broaden infrastructure for the entire industry and academia

17. Thank You