Tom McMullen Period 3 Week 9 8/4/2013 – 12/4/2013

LETI wafer thinning project flow Phase 1 and 2 Technology Run DescriptionTimeline Month 9 (5 th Aug – 30 th Aug) Week ETET of Assemblies bump bond yeild Deliverables D11D12 Current Week On Target Off Target Target Date to be confirmed upon Advacam delivery schedual Technology Run DescriptionTimeline Period 1 (4 th Feb - 1 st Mar) 2 (4 th Mar – 29 th Mar) 3 (1 st Apr – 26 th Apr) 4 (29 th Apr – 3 rd May) 5 (6 th May – 31 st May) 6 (3 rd Jun – 28 th Jun) 7 (1 st Jul – 26 th Jul) 8 (29 th Jul – 2 nd Aug) Week Design µ-bumps layout and mask delivery TR1 First two wafers non-thinned to confirm LETI µ- bumps Wafer ID VMB8WDH V6B8WUH TR2 Second 2 wafers thinned to 100um VUAYCRH ABPJXGH TR3 Third 2 wafers thinned to 100 µm with first estimate of BS compensation VKB8WFH TR4 Fourth 2 wafers with further precise BS compensation TBS TR5 Fifth 2 wafers with final BS compensation for stacking TBS SMCWafer Bow Measurements ADVACAMFlip chip assemblies ETET of assemblies bump yield Deliverables D1D1 D2 D3D4D5 D6D7 D8D9 D10

LETI wafer thinning project flow Phase 1 and 2  D1 – Mask design and delivery  D2 – Technology run 1: First set of 2 wafers at full thickness and fully processed with µ- bumps  D3 – Technology Run 2: Second set of 2 wafers thinned to 100µm and fully processed with µ-bumps (no backside processing) delivered to SMC for thermal cycling bow measurements.  D4 – Technical report on bow/stress measurements.  D5 – Technical report on electrical test, feedback on µ-bumps yield maps  D6 – Technology Run 3: Third set of 2 wafers thinned to 100µm and fully processed with µ-bumps and with first estimate of back-side stress compensation. Delivered to SMC for thermal cycling bow measurements.  D7 – Technical report on bow/stress measurements.  D8 – Technology Run 5: Fourth set of 2 wafers thinned to 100µm and fully processed with µ-bumps and having an optimised back-side stress compensation layer. Delivered to SMC for thermal cycling bow measurements.  D9 - Technical report on bow/stress measurements.  D10 – Technology Run 5: : Fifth set of 2 wafers thinned to 100µm and fully processed with µ-bumps and having an optimised back-side stress compensation layer.  D11 – Technical Report on electrical test for optimised stress compensation on wafers thinned to 100µm  D12 – Full project technical report

Action List Phase 1 and 2 ActionWhatWhoWhenComment 7Bow measurement set-upTMcM31/2/2013visit SMC and set up program for bow measurement 9Assembly probe test solutionTMcM19/3/2013Pobe test solution for flip-chipped assemblies - yield maps 10FEI4B probe card and probe set-upRbates/TMcM19/3/2013FEI4B test solution for assembly testing yeild maps 11Experience with FEI4A probe card set-upRbates/TMcM19/3/2013 FEI4A probe card set-up and testing of assemblies on Wentworth 12 Source other suppliers of wafer bow measurementsTMcM29/3/2013Ongoing. Requested update from SMC on FSM coming online

Highlights and issues  LETI have an issue processing wafers at the moment as their Argon sputter clean is down in copper PVD tool and will delay the shipment of technology run 1 till the 15 th of April It is essential we run with a sputter etch prior to copper deposition as without it would most likely result in poor electrical contact New estimated completion time 26 th April Bump mask is out of alignment by 20um in both x and y-directions ○ This could be the result of the stepper off-set in IBM that we were informed about but no figure was supplied ○ LETI will align to the pads and don’t foresee any down-line issues for flip-chip alignment ○ LETI will supply alignment measurements post exposure to confirm this ○ There maybe a few more days delay due to this.  Meeting required to discuss sensor availability for the flip-chip process Amount of sensors for flip-chipping – good statistical analysis required for micro-bump yield – Richard and I have begun discussions on this. ○ List has been made by Richard just awaiting the file ○ Received file will discuss with Richard tomorrow and link in for next week’s report FEI4b Assembly testing ○ FEI4b probe card required ○ Test equipment/apparatus required ○ Semi-auto testing solution required for assemblies

Highlights and issues (Cont’d)  SMC FSM thermal cycling tool is out of use at the moment. I have given them dates for when the tool is needed and asked for assurance that the tool will be ready by this time. Feedback from SMC is that they hope to have the tool running for when we require it, but have given no guarantees as yet. ○ I have asked SMC to keep me updated on the progress of this Sourcing alternatives ○ Southampton only have this ability to 150mm ○ JEMFIRE is another possibility

Wafer Inventory Wafer #Wafer IDYield (60 chips max)PurposeComment 1VMB8WDHG= 34, y=17, R=8, B=1Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 2V6B8WUHG= 43, y=13, R=4, B=0Full thickness micro-bump testDelivered to LETI. High-yielding die. Micro-bump yeild testing on assemblies 3VUAYCRH First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 4ABPJXGHG=28, Y=24, R=8 First technology run. Run 2 Received at Glasgow Wafer thinning to 100microns. Used for thermal cycling bow measurements at SMC. Ship to LETI. Shipped to LETI 5 Second technology run. Run 3Wafer identified and will be shipped from CERN to LETI. Awaiting wafer ID and yield 6 Second technology run. Run 3Wafer identified and will be shipped from CERN to LETI. Awaiting wafer ID and yield 7 Third technology run. Run 4Wafer to be identified and delivered to glasgow 8 Third technology run. Run 4Wafer to be identified and delivered to glasgow 9 Forth technology run. Run 5Wafer to be identified and delivered to glasgow 10 Forth technology run. Run 5Wafer to be identified and delivered to glasgow