Specifications & motivation 2  Lowering integration time would significantly reduce background  Lowering power would significantly reduce material budget UPPER LIMIT lower much better ! Nr of bits to code a hit : 35 Fake hit : /event Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Status  Low power :  Front-end (20.5nA/pixel), shaping(a few μs) determines integration time  Data driven readout (see Cesar’s presentation)  Two early submissions + Two engineering runs shared with the other groups. Present engineering run delayed to April 9 th.  Several chips:  Explorer : sequential analog readout for pixel sensor optimization  Investigator : parallel fast (~10ns rise time) analog readout for pixel sensor optimization  pAlpide : small scale (512x64 array of 22x22 micron pixels) prototypes to optimize circuit  pAlpide_fs : full scale prototype (1024x512 of 28x28 micron pixels) prototype for system studies 3 Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

 Analog readout for pixel characterization  Readout time decoupled from integration time  Possibility to reverse bias the substrate  Sequential readout with correlated double sampling  Contains two 1.8x1.8mm 2 matrices of 20x20 and 30x30 micron pixels with different geometriesExplorer 4 PULSED ROWS Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Explorer-1 (April 2013) vs Explorer-0 (July 2012) 5 Comparison of 55 Fe cluster signal for Explorer-0 and Explorer-1 Explorer-1 shows ~ 2x signal increase, and similar noise level Confirms correction on input capacitance, circuit contribution reduced from ~4.6 fF to ~2 fF Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Efficiency & fake hit rate (Explorer-0) 6  High efficiency at low fake hit rates  Reverse substrate bias gives extra margin Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Efficiency & fake hit rate (Explorer-1) 7 Explorer-1 results after tests with electrons at DESY, averaged on all diode geometries after irradiation drop of % in CCE, recovered with back bias better performance of larger diodes with larger spacing to electronics wider distance  wider depletion volume  lower input capacitance better performance of 20 x 20 µm 2 at low back bias voltage detection efficiency above 99% up to 10σ cut, also after irradiation Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

pALPIDE pixel circuit diagram 8 Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 Memory cell, hit enabled during the strobe window. Priority encoder – Reset decoder: only zero-suppressed data are transferred to the periphery. Low Power Analog Front End (< 40 nW/pixel) based on a single stage amplifier/current comparator. Pixel State Register Priority encoder state reset STROBE set Front-end output pulse  Circuit capacitance is even smaller than on explorer 1.  First prototype pAlpide-0 works, but two issues:  Source to nwell diode of transistor inside collection electrode competes with resetting diode, “fixed” with light (> 10fA/pixel !!)  Amplifier/comparator stops working for reverse substrate biases > 2 V, due to loss of inversion in NMOS capacitor => could not operate at minimum sensor capacitance  Note: doubling the Pixel State Register significantly reduces dead time (cfr Adam’s simulations)

pALPIDE first results 9  Minimum detectable charge <130 e-  At nominal bias (20.5 nA/pixel) and threshold setting:  Threshold spread 17 e-  Noise ~ 7 e-  99.6% efficiency in beam test Analog output of one pixel under 55 Fe Noise Threshold Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

pALPIDEfs Low Power Front-End 10 Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March 2014 Fixes for two issues:  Input PMOS transistor outside collection electrode (also for pAlpide1)  Replace for some sectors resetting diode with PMOS transistor Cost: additional capacitance, will have to evaluate impact  Implement capacitor with PMOS instead of NMOS  Also for faster clipping PMOS instead of NMOS clipping transistor Still exploring other alternatives in pAlpides: avoid/minimize the penalty of additional capacitance, further reduce shaping time

pALPIDEfs reset scheme Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March SectorColumns nwell diameter spacing pwell opening Reset 10 to 2552 µm1 µm4 µmPMOS 2256 to 5112 µm 6 µmPMOS 3512 to 7672 µm 6 µmDiode 4768 to µm4 µm10 µmPMOS PMOS reset Diode reset Collection electrode example Pulsing capacitor: 160 aF Input routing line Input PMOS pwell opening = nwell diameter + 2. spacing Please note that in pALPIDE_fs the nwell is octagonal and the p + ring is squared

pALPIDE_fs: 30x15.3mm 1024x512 pixels mm 15.3 mm Pads over the matrix

PADs over matrix: pixel routing 4 metals only  Region of 8x8 pixels allocated for pad over matrix  Provide by-pass for row select and power routing  First results on explorer with metal pads over the matrix promising  Large design effort 13 8 x 28 µm = 224 µm Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Periphery 14 Matrix DACs Readout I/O pads

Pixels and Priority Encoders 15 Priority Encoder Analog Routing

Readout and I/O pads 16

Investigator 17 Thanushan Kugathasan - WP3, ITS-MFT mini-week, 10 March mini-matrices Each mini-matrix has 8x8 pixels. 64 analog outputs to read all the pixels in a mini-matrix. Different pixel designs: Pixel width: from 20 x 20 um 2 up to 50 x 50 um 2 Input transistor inside/outside collection n- well Continuous diode reset and active PMOS switch reset Deep-p-well (minimum and maximum) 5.0 mm x 5.8 mm

Present engineering run: expected April 9th 18  CERN/INFN/WUHA N/YONSEI  pALPIDE_fs  pALPIDE (3)  EXPLORER (3)  INVESTIGATOR  TEST STRUCTURES  RAL  CHERWELL3  2 OTHER TEST CHIPS  IPHC  2 AROM  1 OTHER CHIP Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014

Conclusions  Low power front-end (20.5nA/pixel) with data-driven readout, integration time of a few μs determined by shaping time of the front end  Analog: 20mW/4.5cm 2, digital not optimized (100mW+200mW)/4.5cm 2 for total chip, serializer to be added  This year one more submission for a further iteration before final decision  Full scale chip : Currently defining features, including interface (see Gianluca’s presentation)  Several additional building blocks (also on separate test chips):  Bandgap reference & temperature sensor (Nikhef)  Biasing DAC (Yonsei &CERN, already done for first pALPIDE_fs)  Monitoring ADC (INFN, Yonsei, CERN)  Serializer (with PLL) & LVDS driver (INFN) (see Gianni’s presentation)  pAlpide(s) : further front-end optimization (reduce C and shaping time)  Investigator & Explorer : further sensor optimization if needed  Front-end & sensor: Benefit of low C clearly established, still measuring different structures and starting materials, issues with front end have forced us to take a penalty for pALPIDE_fs, still exploring further improvements also for reduced shaping time  For further details on digital part, see Cesar’s and Alberto’s presentations 19 Walter Snoeys - WP3, ITS-MFT mini-week, 10 March 2014