2. General status and plan Carried out extensive testing, obtained working pixels and promising radiation tolerance, just submitted engineering run 2013 : optimize pixel structure and study different options for the readout architecture to obtain medium/large scale demonstrator 2014 : finalize full scale to be ready for volume production 2 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

3. PIXEL REQUIREMENTS 3  0.3-0.5 W/cm2 power budget is upper limit  Lowering power would significantly reduce material budget ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

4.  Analog:  Determined by collected charge over capacitance (Q/C) in the pixel => pixel sensor optimization  Digital:  Determined by on-chip architecture & cluster size  Architecture:  Rolling shutter: pursued by RAL and by IPHC  Other architectures with in-pixel binary front-end (CERN):  Priority encoder  Orthopix (several projections in addition to X and Y)  Data transmission off-chip:  Determined by cluster size unless data reduction by clustering algorithm Power consumption: 3 components 4 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

6. 6

7. MIMOSA32 chips 7  Characterization measurements with:  55 Fe source (double peak at ~1640 electrons)  Testbeam: 6 GeV π - in T10 from PS  Note: Signal from MIP in 18 micron thick epitaxial layer 80*18=1440 electrons  Extracted values:  Noise in electrons  Signal to Noise Ratio (SNR)  Cluster size  Charge Collection Efficiency (CCE) ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

8. MIMOSA32 chips: Results 55 Fe measurements P7: Dnwell (sq. ~20 μm2), 3T_ll, ELT P2: Nwell_1 (octo, ~10.9 μm2), 3T_ll, ELT P7 V ADC = 1350 mV P2 V ADC = 1350 mV Chip Structur e Noise (e - )CCE seedCCE clusterCluster Size Mean cluster size 9B P721,451,299,352,9 P219,146,497,153,5 8 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

9. MIMOSA32 chips: Variation of V diode 9 V diode up to 1.3 V: Shift of the spectrum towards higher ADC values V diode larger than 1.4 V: No big differences observed Results from Strasbourg confirmed Example: - Chip: 9B - Structure: P00 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

10.  Results on first prototype designed by IPHC Strasbourg promising, significant variation as a function of diode bias  Submitted another prototype to study and optimize pixel  Contains two 1.8x1.8mm matrices of 20x20 and 30x30 micron pixels with different geometries for the collection electrode and surroundings  First measurements see below Prototype July 2012 submission: Explorer0 10 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

11. Floorplan July submission revisited Pixel matrix 90x90 20x20um pixels Analog : current mirrors/buffer/pulsing Digital circuit to control readout Pads 1. 2x2 octogonal 2. 3x3 octogonal 3. 4x4 octogonal 4. 3x3 square 5. 3x3 octo midspace 6. 3x3 octo maxspace 7. 2x2 octo max+space tw 8. 3x3 octogonal tw 9. 3x3 octo maxspace tw Green: pulsed rows (2 per submatrix) 1 4 7 2 5 8 3 6 9 Pixel matrix 60x60 30x30um pixels 1 4 7 2 5 8 3 6 9 11 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

12. More detail on the collection electrodes 12 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

13. Fe-55 spectrum 13 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

14. Fe-55 spectrum 14 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

15. Fe-55 spectrum 15 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

16. Fe-55 spectrum 16 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

17. Fe-55 spectrum 17 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

18. Fe-55 spectrum 18 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

19. Fe-55 spectrum 19 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

20. Fe-55 spectrum 20 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

21. Extracted capacitance (assuming the collection of 1640 electrons) < 5 fF 21 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

22. Cluster sizes 22 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

23. Cluster sizes 23 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

24. Cluster sizes 24 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

25. Cluster sizes 25 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

26. Cluster sizes 26 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

27. Cluster sizes 27 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

28. Cluster sizes 28 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

29. Cluster sizes 29 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

30. Testbeam setup 30 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

31. Landaus 31 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

32. Efficiency & fake hit rate (explorer chip) 32 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013  High efficiency at low fake hit rates  Reverse substrate bias gives extra margin

33.  Observed:  Fully functional pixels  MPV increase and cluster size decrease with increasing back bias  Cluster size increase with decreasing collection electrode size  MPV is not affected by pixel size, but increases at low biases with decreasing collection electrode size and increasing spacing  Very high efficiencies with very low hit rates  Capacitance contribution from routing: 2.1fF, full circuit with routing = 4.6 fF  Less than 5 fF total at -8 V for some pixels => detector capacitance less than 1 fF  Can reduce circuit contribution to reach ~1-2 fF total  Done for engineering run which is now being submitted Explorer chip (July 2012 submission) 33 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

34. Further pixel sensor improvement 34  For the July 2012 submission we obtain ~50mV per hit but distributed over several pixels, and optimization should give at least a factor of 2  Could we reach “digital signal” (250mV) on a single pixel and save more power? Several options:  Thicker epi/high resistivity substrate will increase signal  Lower doping/higher resistivity for more depletion (in combination with reverse substrate bias) and lower cluster size/multiplicity  Further lowering input capacitance  … ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

36. IN PIXEL HIT DISCRIMINATION 36 VRESET  Large gain amplifier/comparator discharges ~ 80fF storage capacitor when the sensor receives a particle hit  Storage capacitor instead of full flip-flop to save space  Allows other readout architectures AMPL/CO MP ENABLE RESET ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

37. Front-End and Memory layout 37 Block Size: 10.5 x 22.0 µm 2 Memory size: 6.9 x 7.3 µm 2 Custom shape NMOS cap with L > 10 um Circuitry in deep pwell (except the collection electrode) ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

38. Output signal example 38 65 105 123 250 8000 Qin (electrons) Time walk ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

39. Minimum detectable charge 39 Minimum detectable charge definition Minimum detectable charge as a function of the bias current Cd = 1 fF Ith = 0.5 nA Ileak = 5 pA Noise at threshold 14e (nominal 20nA condition) Memory state (V) Qin (electrons) ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

41.  RAL & Strasbourg:  Rolling shutter architecture  Strasbourg also in-pixel discriminator/ADC  CERN :  Digital architectures requiring low power front end with discriminator in the pixel  Priority encoder:  Multiple projections (orthopix)Architecture 41 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

42. Priority Encoder readout 42  Data driven readout of the pixel matrix, only zero-suppressed data are transferred to the periphery.  Asynchronous circuit with no clock propagation into the pixel matrix:  Power reduction.  Noise reduction (no clock disturbance in to the analog part). End of Column logic Pixels arranged in columns Layout view digital analog separate address bus per column Each clock cycle the memory of the pixel with the highest priority is reset and its address is sent to the periphery. ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

43. Priority Encoder – Pixel layout 43 12 µm + 10 µm 22 µm Collection electrode Part of Priority Encoder Analog Front End Memory cell Analog Front End Memory cell Collection electrode Priority encoder reset state ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

44. IMPLEMENTATION IN ENGINEERING RUN 44  Mxt_CERN1...4  In total  4 variants of priority encoder matrix  16 explorer matrices  Several test structures PRIORITY ENCODER EXPLORER TEST ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

45. ORTHOPIX 45  Based on multiple projections to reduce ambiguities  Already four well chosen projections X, Y, U and V yield good reconstruction results for outer layers  Allows data (and power) reduction : for four projections data reduced from N^2 pixels to 4N signals  2 255x255 pixel matrices + one smaller matrix implemented in engineering run  NOTE: LVDS driver/receiver ORTHOPIX LVDS TEST ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

46. SEUCHIP 46  Contains array of single port, dual port memory and shift register  Allows Single Event Upset testing ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

48. March 2013 engineering run 48  CERN/INFN/WUHAN: explorer, priority encoder and orthopix matrix in several variants and test structures  Two variants of LVDS driver  RAL: three matrices with rolling shutter  IPHC: many matrices with rolling shutter, also significant work on zero suppression circuitry.  Several starting materials: P. Riedler  Engineering run will require very significant test program => will need to plan ahead ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

50. Total Ionizing Dose test on transistors 50 X-Ray tube ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

51. Example: low voltage NMOS transistor 51 I 0 = 100 nA. W/L TID (Mrad) W/L = 0.22 um / 0.18 um -> I 0 = 122.2 nA  Curves do not change significantly with irradiation  Extensive testing campaign on transistors now almost complete and radiation tolerance in excess of ALICE needs ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

52. RADIATION TOLERANCE (1Mrad + 10 13 n/cm 2 ) 52 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013  Signal not changed, noise increased as expected  Neutron and proton irradiated explorer samples give promising results, analysis in progress

54. DESIGN TOWARDS FULL CHIP/SYSTEM 54  Would like to submit simplified large scale chip in July, important for system aspects  Need to design/debug/optimize several circuit blocks (see next slide) and would like to submit a more complex large scale chip towards the end of the year ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

55. DESIGN TOWARDS FULL CHIP/SYSTEM 1) Pixel sensor optimization: CERN/WUHAN 2) Pixel matrix: CERN/WUHAN 3) Digital readout circuitry in the periphery: INFN 4) Serializer/LVDS driver: INFN 5) Power regulation: some interest from NIKHEF 6) On-chip pulser for self-test 7) Configuration and Monitoring 1) SEU tolerant registers + I/O 2) DAC for bias 3) ADC for monitoring 4) Monitoring: Temperature, Power consumption, Detector leakage, chip ID STILL SIGNIFICANT MANPOWER NEEDED, especially in 5-7 but also in 1-4 55 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

56. TESTING 56  This year we will receive many different pixels  different starting materials  different anode geometries  Different frontends  Different readout architectures  We need to characterise them for  Noise behavior (low noise setup)  Charge collection efficiency (radioactive sources)  Position dependent efficiency (laser light)  Detection efficiency (test beam)  Radiation hardness (all tests above after irradiation)  Distribution of work (and electrical test systems) amongst institutes is extremely important  Perhaps we will already have the first module assemblies ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

57. COMMON TEST SYSTEM DEVELOPMENT 57 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

58. COMMON TEST SYSTEM DEVELOPMENT 58 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

59. TESTING 59 MIMOSA32 MIMOSA34 Explorer-0 Explorer-1 CHERWEL L2 CERN digital readout SEU NoiseN/A Fe-55N/A Test beam LaserN/A All before and after irradiation (neutrons, X-ray) ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

60. CONCLUSIONS 60  Pixel sensor  50mV distributed over a few pixels, with prospect of at least 2x improvement  Could we get to digital signal by further optimization?  Analog front end design: 40nW*250 000 pixels = 10 mW/cm 2  Digital: looking at solution around 10mW/cm 2  Off-chip data transmission ~ 30-50mW/chip or <10mW/cm 2 Trying to approach strip level power consumption per unit area and definitely stay below 100mW/cm 2  Radiation tolerance sufficient for Alice  Significant work in design and in test participation needed ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

61. 61 THANK YOU ! ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

62. Transient Noise 62 t = 200 ns : hit t = 50 us : sample and reset Analog Output Memory State Memory state samples histogram Repeated every 50 us ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

63. Noise - Error Function Fit 63 Qin (electrons) Memory on state 1 rate µ = 106.7 electrons σ = 13.8 electrons Ibias = 20 nA Cd = 1 fF ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

64. Noise vs. detector capacitance 64 CdIbiasIthrIleakQthNoiseSNR@ thr 1 fF20 nA500 pA5 pA105 e - 14 e - 7.5 5 fF20 nA500 pA5 pA260 e - 27 e - 9.6 5 fF50 nA250 nA5 pA133 e - 20 e - 6.7 5 fF50 nA250 nA1 nA129 e - 18 e - 7.2 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

65. MOS transistor matching 65 Extracted value from simulation NMOS: A Vth = 3.43 mV µm PMOS:A Vth = 3.25 mV µm Monte Carlo simulation in ADE XL environment for mismatch statistical variation. Process statistical variation seems to be not available. ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

66. Noise vs. detector capacitance 66 µ = 104.6 electrons σ = 3.0 electrons Memory on state 1 rate Ibias = 20 nA Cd = 1 fF ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013

67. RADIATION TOLERANCE (ionizing 3 Mrad) 67 ALICE ITS UPGRADE MEETING – Seoul, April 5-6, 2013