TODAY’S OUTLINE Finite State Machine Exercise 1 Exercise 1 Exercise 2 Exercise 2 Exercise 3 Exercise 3 Exercise 4 Exercise 4.

Slides:



Advertisements
Similar presentations
Digital System Design-II (CSEB312)
Advertisements

//HDL Example 8-2 // //RTL description of design example (Fig.8-9) module Example_RTL (S,CLK,Clr,E,F,A);
Counters Discussion D8.3.
Traffic light contoller using FSM
Verilog in transistor level using Microwind
Combinational Logic.
Table 7.1 Verilog Operators.
//HDL Example 5-1 // //Description of D latch (See Fig.5-6) module D_latch (Q,D,control); output Q; input.
Verilog. 2 Behavioral Description initial:  is executed once at the beginning. always:  is repeated until the end of simulation.
FSM Revisit Synchronous sequential circuit can be drawn like below  These are called FSMs  Super-important in digital circuit design FSM is composed.
//HDL Example 6-1 // //Behavioral description of //Universal shift register // Fig. 6-7 and Table 6-3 module shftreg.
How to get a Circuit in verilog converted to hspice, connected to the micron package models, and simulating in hspice and hsimplus.
Digital Electronics Chapter 5 Synchronous Sequential Logic.
Slide 1 7. Verilog: Combinational always statements. VHDL: Combinational Processes: To avoid (I.E. DO NOT What in your HDL code?) Cases that generate Synthesis.
CSE Spring Verilog for Sequential Systems - 1 Today: Verilog and Sequential Logic zFlip-flops yrepresentation of clocks - timing of state.
FSM examples.
Spring 20067W. Rhett Davis with minor modifications by Dean Brock ECE 406 at UNASlide 1 ECE 406 Design of Complex Digital Systems Lecture 10: 9: State.
ELEN468 Lecture 101 ELEN 468 Advanced Logic Design Lecture 10 Behavioral Descriptions IV.
Pulse-Width Modulated DAC
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
Digital System Design by Verilog University of Maryland ENEE408C.
Verilog Sequential Circuits Ibrahim Korpeoglu. Verilog can be used to describe storage elements and sequential circuits as well. So far continuous assignment.
ELEN 468 Lecture 161 ELEN 468 Advanced Logic Design Lecture 16 Synthesis of Language Construct II.
Ring Counter Discussion 11.3 Example 32.
Prof. John Nestor ECE Department Lafayette College Easton, Pennsylvania ECE Senior Design I Lecture 4 - Verilog 2 (Sequential.
ENEE 408C Lab Capstone Project: Digital System Design Fall 2005 Sequential Circuit Design.
COE 202 Introduction to Verilog Computer Engineering Department College of Computer Sciences and Engineering King Fahd University of Petroleum and Minerals.
Advanced Verilog EECS 270 v10/23/06.
FSMs in Verilog and other random things 9/27/02. FSM structure CLK STATE Next State Logic Inputs Output Logic Outputs.
D Flip-Flops in Verilog Discussion 10.3 Example 27.
Sequential Logic in Verilog
ECE 551 Digital System Design & Synthesis Fall 2011 Midterm Exam Overview.
Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Ders 8: FSM Gerçekleme ve.
Lab7-1 Lab 6: FSM Description Separate combinational and memory circuits –State memory uses FFs –Others are combinational circuits.
ECE/CS 352 Digital System Fundamentals© 2001 C. Kime 1 ECE/CS 352 Digital Systems Fundamentals Spring 2001 Chapters 3 and 4: Verilog – Part 2 Charles R.
Register Transfer Level & Design with ASM
Telephone Etiquette By Taylor Smith. What To Expect….. How to Answer How to be Prepared What to say What not to say How to leave a message.
Telephone Manners.  “Take a music bath once or twice a week for a few seasons, and you will find that it is to the soul what the water bath is to the.
GET CONNECTED Move Ahead 7 th form VOCABULARY WORK Let’s refresh the words. Read the questions and use the new words in your answers.
Verilog for Synthesis Ing. Pullini Antonio
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Verilog Part 3 – Chapter.
Finite State Machine (FSM) Nattha Jindapetch December 2008.
Making a phone call. Introducing yourself Asking to speak to somebody Asking who the caller is Telling the caller that someone is not available Taking.
The UNIVERSITY of NORTH CAROLINA at CHAPEL HILL State Machines Anselmo Lastra.
Digital Electronics.
Chapter 11: System Design Methodology Digital System Designs and Practices Using Verilog HDL and 2008, John Wiley11-1 Chapter 11: System Design.
OUTLINE Introduction Basics of the Verilog Language Gate-level modeling Data-flow modeling Behavioral modeling Task and function.
ACCESS IC LAB Graduate Institute of Electronics Engineering, NTU 99-1 Under-Graduate Project Design of Datapath Controllers Speaker: Shao-Wei Feng Adviser:
SYEN 3330 Digital SystemsJung H. Kim Chapter SYEN 3330 Digital Systems Chapters 4 – Part4: Verilog – Part 2.
Lab5-1 張明峰 交大資工系 Lab 5: FSM and BCD counters Implement the vending machine of lab 2 A two-digit BCD counter –two BCD counters –can load data in parallel.
1 Workshop Topics - Outline Workshop 1 - Introduction Workshop 2 - module instantiation Workshop 3 - Lexical conventions Workshop 4 - Value Logic System.
EMT 351/4 DIGITAL IC DESIGN Verilog Behavioral Modeling  Finite State Machine -Moore & Mealy Machine -State Encoding Techniques.
Pusat Pengajian Kejuruteraan Mikroelektronik EMT 351/4 DIGITAL IC DESIGN Verilog Behavioural Modeling (Part 4) Week #
1 Lecture 3: Modeling Sequential Logic in Verilog HDL.
Figure Implementation of an FSM in a CPLD..
Exp#7 Finite State Machine Design in Verilog COE203 Digital Logic Laboratory Dr. Ahmad Almulhem KFUPM Spring 2009.
Supplement on Verilog for Algorithm State Machine Chart
Figure 8.1. The general form of a sequential circuit.
Lecture L5.1 Mealy and Moore Machines
Supplement on Verilog Sequential circuit examples: FSM
ECEN 248 Lab 9: Design of a Traffic Light Controller
Digital Logic Design Digital Design, M. Morris Mano and Michael D
Leaving messages on answer machines
HDL Compiler Unsupport (Do NOT use in your verilog code)
FSM MODELING MOORE FSM MELAY FSM. Introduction to DIGITAL CIRCUITS MODELING & VERIFICATION using VERILOG [Part-2]
COE 202 Introduction to Verilog
6. Registers and Counters
Supplement on Verilog Sequential circuit examples: FSM
The Verilog Hardware Description Language
Presentation transcript:

TODAY’S OUTLINE Finite State Machine Exercise 1 Exercise 1 Exercise 2 Exercise 2 Exercise 3 Exercise 3 Exercise 4 Exercise 4

Exercise 1

Solution 1 module FSM1 (reset, brake, accelerator, clock, constant_speed, decelerating, accelerating ); input reset, brake, accelerator, clock; output constant_speed, decelerating, accelerating ; reg constant_speed, decelerating, accelerating ; parameter S0 = 2'b00; parameter S1 = 2'b01; parameter S2 = 2'b10; parameter S3 = 2'b11; reg [1:0] state, next_state; (posedge clk) begin case (state) S0: begin if (!brake && accelerator) begin next_state = S1; {accelerating,constant_speed,decelerating} = 3’b100; end else if (brake) begin next_state = S0; {accelerating,constant_speed,decelerating} = 3’b010; end

Cont.. S1: begin if (!brake && accelerator) begin next_state = S2; {accelerating,constant_speed,decelerating} = 3’b100; end else if (brake) begin next_state = S0; {accelerating,constant_speed,decelerating} = 3’b001; end S2: begin if (!brake && accelerator) begin next_state = S3; {accelerating,constant_speed,decelerating} = 3’b100; end else if (brake) begin next_state = S1; {accelerating,constant_speed,decelerating} = 3’b001; end

Cont.. S3: begin if (!brake && accelerator) begin next_state = S3; {accelerating,constant_speed,decelerating} = 3’b100; end else if (brake) begin next_state = S2; {accelerating,constant_speed,decelerating} = 3’b001; end default: begin next_state = S0; {accelerating,constant_speed,decelerating} = 3’b000; end endcase end clk or posedge reset) begin if (reset) state <= S0; else state <= next_state; end endmodule

Exercise 2 State Transition Table PS (Present State) NS (Next State) Output (Y) X = 0 X = 1 X = 0 X = 1 AAB00 BCD00 CAD00 DEF01 EAF11 FGF11 GAF01

Exercise 3 State Transition Table PS (Present State) NS (Next State) Output (Y) X = 0 X = 1 AAB0 BCD0 CAD0 DEF1 EAF1 FGF1 GAF1

Exercise 4 Sequence of events when you answer the telephone. We begin the process by waiting for the telephone to ring; during this time, we are in a wait state, (designated W) We begin the process by waiting for the telephone to ring; during this time, we are in a wait state, (designated W) When the phone rings, you pick up the handset and change to the answer state (designated A). When the phone rings, you pick up the handset and change to the answer state (designated A). At this point, one of four things may happen: At this point, one of four things may happen: the person making the call asks for you; the person making the call asks for you; the person making the call asks for someone who is currently at home; the person making the call asks for someone who is currently at home; the person making the call asks for someone who is currently not at home; the person making the call asks for someone who is currently not at home; it is a wrong number. it is a wrong number. If the call is for you, you say hello and change to the talking state (designated T). If the call is for you, you say hello and change to the talking state (designated T).

Cont.. If the call is for someone who is currently at home, you tell the person making the call to wait and move to a state where you are getting the person they desire (designated G). If the call is for someone who is currently at home, you tell the person making the call to wait and move to a state where you are getting the person they desire (designated G). If the call is for someone who is currently not at home, you tell the caller and change to the state where you are taking a message (designated M). If the call is for someone who is currently not at home, you tell the caller and change to the state where you are taking a message (designated M). If it is a wrong number, you tell the caller and move to the state where the call is finishing (designated F). If it is a wrong number, you tell the caller and move to the state where the call is finishing (designated F). Once in the talking state, whenever the caller talks you reply and stay in the talking state. Once in the talking state, whenever the caller talks you reply and stay in the talking state.

Cont.. If however, the caller says goodbye, you say goodbye and move to the finish state. If however, the caller says goodbye, you say goodbye and move to the finish state. If you were in the state where you were getting someone else to come to the phone, when they If you were in the state where you were getting someone else to come to the phone, when they arrive they say hello and enter the talking state. If you are taking a message and the caller says goodbye, you say goodbye and move to the finish state. If you are taking a message and the caller says goodbye, you say goodbye and move to the finish state. Once in the finish state, when the caller hangs up, you hang up the handset and change to the wait state. Once in the finish state, when the caller hangs up, you hang up the handset and change to the wait state.

Next week Lab 4 (Finite State Machine) Do some homework… That’s all for today. See u on Tuesday….