1. Placement of Digital Microfluidic Biochips Using the T-tree Formulation Ping-Hung Yuh 1, Chia-Lin Yang 1, and Yao-Wen Chang 2 1 Dept. of Computer Science.

Slides:



Advertisements
Similar presentations
Optimal Bus Sequencing for Escape Routing in Dense PCBs H.Kong, T.Yan, M.D.F.Wong and M.M.Ozdal Department of ECE, University of Illinois at U-C ICCAD.
Advertisements

Force-Directed List Scheduling for DMFBs Kenneth ONeal, Dan Grissom, Philip Brisk Department of Computer Science and Engineering Bourns College of Engineering.
A Graph-Partitioning-Based Approach for Multi-Layer Constrained Via Minimization Yih-Chih Chou and Youn-Long Lin Department of Computer Science, Tsing.
1 Advancing Supercomputer Performance Through Interconnection Topology Synthesis Yi Zhu, Michael Taylor, Scott B. Baden and Chung-Kuan Cheng Department.
X-Architecture Placement Based on Effective Wire Models Tung-Chieh Chen, Yi-Lin Chuang, and Yao-Wen Chang Graduate Institute of Electronics Engineering.
Modern VLSI Design 3e: Chapter 10 Copyright  2002 Prentice Hall Adapted by Yunsi Fei ECE 300 Advanced VLSI Design Fall 2006 Lecture 24: CAD Systems &
Optimal Testing of Digital Microfluidic Biochips: A Multiple Traveling Salesman Problem R. Garfinkel 1, I.I. Măndoiu 2, B. Paşaniuc 2 and A. Zelikovsky.
Paul Falkenstern and Yuan Xie Yao-Wen Chang Yu Wang Three-Dimensional Integrated Circuits (3D IC) Floorplan and Power/Ground Network Co-synthesis ASPDAC’10.
Coupling-Aware Length-Ratio- Matching Routing for Capacitor Arrays in Analog Integrated Circuits Kuan-Hsien Ho, Hung-Chih Ou, Yao-Wen Chang and Hui-Fang.
FPGA Latency Optimization Using System-level Transformations and DFG Restructuring Daniel Gomez-Prado, Maciej Ciesielski, and Russell Tessier Department.
Droplet-Aware Module-Based Synthesis for Fault-Tolerant Digital Microfluidic Biochips Elena Maftei, Paul Pop, and Jan Madsen Technical University of Denmark.
An Optimal Algorithm of Adjustable Delay Buffer Insertion for Solving Clock Skew Variation Problem Juyeon Kim, Deokjin Joo, Taehan Kim DAC’13.
TH EDA NTHU-CS VLSI/CAD LAB 1 Re-synthesis for Reliability Design Shih-Chieh Chang Department of Computer Science National Tsing Hua University.
Supply Voltage Degradation Aware Analytical Placement Andrew B. Kahng, Bao Liu and Qinke Wang UCSD CSE Department {abk, bliu,
Scheduling with Optimized Communication for Time-Triggered Embedded Systems Slide 1 Scheduling with Optimized Communication for Time-Triggered Embedded.
Storage Assignment during High-level Synthesis for Configurable Architectures Wenrui Gong Gang Wang Ryan Kastner Department of Electrical and Computer.
FPGA Acceleration of Phylogeny Reconstruction for Whole Genome Data Jason D. Bakos Panormitis E. Elenis Jijun Tang Dept. of Computer Science and Engineering.
Jieyi Long and Seda Ogrenci Memik Dept. of EECS, Northwestern Univ. Jieyi Long and Seda Ogrenci Memik Dept. of EECS, Northwestern Univ. Automated Design.
Processing Rate Optimization by Sequential System Floorplanning Jia Wang 1, Ping-Chih Wu 2, and Hai Zhou 1 1 Electrical Engineering & Computer Science.
Tabu Search-Based Synthesis of Dynamically Reconfigurable Digital Microfluidic Biochips Elena Maftei, Paul Pop, Jan Madsen Technical University of Denmark.
Mixed Non-Rectangular Block Packing for Non-Manhattan Layout Architectures M. Wu, H. Chen and J. Jou Department of EE, NCTU HsinChu, Taiwan ISQED 2011.
Area-I/O Flip-Chip Routing for Chip-Package Co-Design Progress Report 方家偉、張耀文、何冠賢 The Electronic Design Automation Laboratory Graduate Institute of Electronics.
NCKU CSIE EDALAB Department of Computer Science and Information Engineering National Cheng Kung University Tainan, Taiwan Tsung-Wei.
CAFE router: A Fast Connectivity Aware Multiple Nets Routing Algorithm for Routing Grid with Obstacles Y. Kohira and A. Takahashi School of Computer Science.
Recent Research and Emerging Challenges in the System-Level Design of Digital Microfluidic Biochips Paul Pop, Elena Maftei, Jan Madsen Technical University.
Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization L. Li, Y. Ma, N. Xu, Y. Wang and X. Hong WuHan.
Network Aware Resource Allocation in Distributed Clouds.
1 SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects Qiang Xu and Yubin Zhang Krishnendu Chakrabarty The Chinese.
1 Modern Floorplanning Based on Fast Simulated Annealing Tung-Chieh Chen* and Yao-Wen Chang* # Graduate Institute of Electronics Engineering* Department.
TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.
An Efficient Clustering Algorithm For Low Power Clock Tree Synthesis Rupesh S. Shelar Enterprise Microprocessor Group Intel Corporation, Hillsboro, OR.
Bus-Driven Floorplanning Hua Xiang*, Xiaoping Tang +, Martin D. F. Wong* * Univ. Of Illinois at Urbana-Champaign + Cadence Design Systems Inc.
Bus-Pin-Aware Bus-Driven Floorplanning B. Wu and T. Ho Department of Computer Science and Information Engineering NCKU GLSVLSI 2010.
Regularity-Constrained Floorplanning for Multi-Core Processors Xi Chen and Jiang Hu (Department of ECE Texas A&M University), Ning Xu (College of CST Wuhan.
1 Exploring Custom Instruction Synthesis for Application-Specific Instruction Set Processors with Multiple Design Objectives Lin, Hai Fei, Yunsi ACM/IEEE.
The Fast Optimal Voltage Partitioning Algorithm For Peak Power Density Minimization Jia Wang, Shiyan Hu Department of Electrical and Computer Engineering.
A Graph Based Algorithm for Data Path Optimization in Custom Processors J. Trajkovic, M. Reshadi, B. Gorjiara, D. Gajski Center for Embedded Computer Systems.
Ping-Hung Yuh, Chia-Lin Yang, and Yao-Wen Chang
SVM-Based Routability-Driven Chip-Level Design for Voltage-Aware Pin-Constraint EWOD Chips Qin Wang 1, Weiran He, Hailong Yao 1, Tsung-Yi Ho 2, Yici Cai.
Tao Lin Chris Chu TPL-Aware Displacement- driven Detailed Placement Refinement with Coloring Constraints ISPD ‘15.
ILP-Based Pin-Count Aware Design Methodology for Microfluidic Biochips Chiung-Yu Lin and Yao-Wen Chang Department of EE, NTU DAC 2009.
Register Placement for High- Performance Circuits M. Chiang, T. Okamoto and T. Yoshimura Waseda University, Japan DATE 2009.
Exact routing for digital microfluidic biochips with temporary blockages OLIVER KESZOCZE ROBERT WILLE ROLF DRECHSLER ICCAD’14.
A SAT-Based Routing Algorithm for Cross-Referencing Biochips Ping-Hung Yuh 1, Cliff Chiung-Yu Lin 2, Tsung- Wei Huang 3, Tsung-Yi Ho 3, Chia-Lin Yang 4,
Resource Mapping and Scheduling for Heterogeneous Network Processor Systems Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinha, Arunabha Sen and Andrea.
Rectlinear Block Packing Using the O-tree Representation Yingxin Pang Koen Lampaert Mindspeed Technologies Chung-Kuan Cheng University of California, San.
Solving the Maximum Cardinality Bin Packing Problem with a Weight Annealing-Based Algorithm Kok-Hua Loh University of Maryland Bruce Golden University.
1 SYNTHESIS of PIPELINED SYSTEMS for the CONTEMPORANEOUS EXECUTION of PERIODIC and APERIODIC TASKS with HARD REAL-TIME CONSTRAINTS Paolo Palazzari Luca.
V. Cacchiani, ATMOS 2007, Seville1 Solving a Real-World Train Unit Assignment Problem V. Cacchiani, A. Caprara, P. Toth University of Bologna (Italy) European.
Reliability-Oriented Broadcast Electrode- Addressing for Pin-Constrained Digital Microfluidic Biochips Department of Computer Science and Information Engineering.
NCKU CSIE EDALAB Tsung-Wei Huang, Chun-Hsien Lin, and Tsung-Yi Ho Department of Computer Science and Information Engineering.
Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,
ILP-Based Inter-Die Routing for 3D ICs Chia-Jen Chang, Pao-Jen Huang, Tai-Chen Chen, and Chien-Nan Jimmy Liu Department of Electrical Engineering, National.
Fast Online Synthesis of Generally Programmable Digital Microfluidic Biochips Dan Grissom and Philip Brisk University of California, Riverside CODES+ISSS.
NCKU CSIE EDALAB Tsung-Wei Huang and Tsung-Yi Ho Department of Computer Science and Information Engineering National Cheng.
1 of 16 April 25, 2006 System-Level Modeling and Synthesis Techniques for Flow-Based Microfluidic Large-Scale Integration Biochips Contact: Wajid Hassan.
1 NTUplace: A Partitioning Based Placement Algorithm for Large-Scale Designs Tung-Chieh Chen 1, Tien-Chang Hsu 1, Zhe-Wei Jiang 1, and Yao-Wen Chang 1,2.
Wajid Minhass, Paul Pop, Jan Madsen Technical University of Denmark
1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp.
ILP-Based Synthesis for Sample Preparation Applications on Digital Microfluidic Biochips ABHIMANYU YADAV, TRUNG ANH DINH, DAIKI KITAGAWA AND SHIGERU YAMASHITA.
Review for E&CE Find the minimal cost spanning tree for the graph below (where Values on edges represent the costs). 3 Ans. 18.
Synthesis of Digital Microfluidic Biochips with Reconfigurable Operation Execution Elena Maftei Technical University of Denmark DTU Informatics
Synthesis of Reliable Digital Microfluidic Biochips using Monte Carlo Simulation Elena Maftei, Paul Pop, Florin Popenţiu Vlădicescu Technical University.
Routing-Based Synthesis of Digital Microfluidic Biochips Elena Maftei, Paul Pop, Jan Madsen Technical University of Denmark CASES’101Routing-Based Synthesis.
1 Double-Patterning Aware DSA Template Guided Cut Redistribution for Advanced 1-D Gridded Designs Zhi-Wen Lin and Yao-Wen Chang National Taiwan University.
COE-571 Digital System Testing A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries Authors: P. Bernardi, M. Grosso, M. Rebaudengo,
Synthesis of Biochemical Applications on Digital Microfluidic Biochips with Operation Variability Mirela Alistar, Elena Maftei, Paul Pop, Jan Madsen.
1 Placement-Aware Architectural Synthesis of Digital Microfluidic Biochips using ILP Elena Maftei Institute of Informatics and Mathematical Modelling Technical.
Architecture Synthesis for Cost Constrained Fault Tolerant Biochips
Elena Maftei Technical University of Denmark DTU Informatics
Presentation transcript:

1

Placement of Digital Microfluidic Biochips Using the T-tree Formulation Ping-Hung Yuh 1, Chia-Lin Yang 1, and Yao-Wen Chang 2 1 Dept. of Computer Science & Information Engineering 2 Graduate Institute of Electronics Engineering and Dept. of Electrical Engineering National Taiwan University, Taiwan

3 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

4 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

5 Digital Microfluidic Biochips Perform laboratory procedures based on liquid particles (droplets) The two main components:  Reconfigurable devices (electrodes) Droplets can move freely on the reconfigurable device  Non-reconfigurable devices (detectors and reservoirs) Only one functionality Reservoirs/Dispensing ports Optical detectorDroplets Electrodes Mixing two droplets The schematic view of a biochip (Duke Univ.) Storage

6 Digital Microfluidic Biochips (cont’d) Time: 1~4 Time: 4~5 Storage Dilution Time: 5~7 Mix Dilution a Mix b Dilution Mix c Task graph

7 Placement Problem of Biochips Inputs:  Sequencing graph  Microfluidic module library  Design specification: Fixed architecture (ex: 5x5-array) and maximum assay completion time (ex: 400 sec) Limited number of non-reconfigurable devices Output: the schedule and placement of tasks a b c d e f Dispense Mix Detection A sequencing graph 301x1 cellOpt. N/A1x1 cellStorage 42x3-array 72x2-arrayMixing TimeAreaResource Microfluidic Module Library

8 Previous Work Architecture-level synthesis (scheduling and binding)  Deng et al, TCAD’01 Architecture-level model and ILP-based method  Su and Chakrabarty, ICCAD’04 Sequencing graph model and two heuristics Physical placement  Su and Chakrabarty, DATE’05 Simulated annealing based algorithm with given scheduled tasks Unified synthesis and placement  Su and Chakrabarty, DAC’05 Parallel recombinative simulated annealing List scheduling and greedy placement method

9 Our Contribution Formulate the execution of a bioassay as a 3D floorplan Apply a tree-based representation (T-tree) to solve the floorplanning/placement problem Time t 1 Mix Storage Mix Dilute Mix Time t 2 Time t 3 Mix Dilute Storage T Y X Mix Storage Dilute

10 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

11 Bioassay Execution to 3D floorplan Model each task and storage as a 3D box Model the execution of a bioassay as a 3D floorplan Biochip placement problem to 3D temporal floorplanning problem Time t 1 Mix Storage Mix Dilute Mix Time t 2 Time t 3 Mix Dilute Storage T Y X Mix

12 Review of T-tree A 3-ary tree representation for temporal floorplanning/placement problem A 3D compacted floorlpan The corresponding T-tree Mix b Dilute c Storages s T Y X Mix a Mix b Mix a Storages s Dilute c

13 Review of T-tree (cont’d) The T-tree keeps the geometric relation as follows:  Left child: adjacent in the T + direction  Middle child: in the Y + direction with the same t- coordinate  Right child: in the X + direction with the same t- and y- coordinates T i : duration of i t i : starting time of i Mix b Dilute c Storage s Mix a Mix b Mix a Storage s Dilute c left child middle child right child t j =t i +T i t k = t i t l = t i i j kl The structure of T-tree

14 Modeling Tasks in a T-tree Model each task as a node in a T-tree Dispense d a b c e f Mix Detection A sequencing graph The corresponding T-tree f ce a b d

15 Modeling Storages Model each storage as a node in a T-tree  Each edge in a sequencing graph represents a storage Dispense d a b c e f Mix Detection A sequencing graph The corresponding T-tree f ce a b d s1s1 s2s2 s3s3 s4s4 s5s5 Storage s1s1 s2s2 s3s3 s4s4 s5s5

16 Modeling Storages (cont’d) The storage constraint: the duration of one storage covers the time gap between two data-dependent tasks Insert a storage node in one of the feasible locations in a T-tree  Ensure that t s = t b + T b Example of feasible locations feasible location b c s t tbtb TbTb left child middle child right child t j =t i +T i t k = t i t l = t i i j kl The structure of T-tree b e a dc s t a =t b +T b t d =t e =t a

17 Modeling the Design Specification The fixed-cube constraint:  Model the fixed architecture and max. completion time as a 3D cube  A feasible floorplan must be within this 3D cube The resource constraint:  # of non-reconfigurable tasks is limited at any time  Add the virtual edges in the sequencing graph Max. completion time Fixed architecture A feasible floorplan a b c d e f Dispense Mix Detection Virtual edge

18 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

19 Floorplanning Algorithm Based on simulated annealing (SA) The modified SA flow:  Detect the violation of the storage constraints  Delete unused storages in a T-tree for packing efficiency Data Dependency Storage Constraint Number of storages Adjustment Feasibility Detection & Tree Reconstruction Perturbation Termination? Yes No Packing

20 Floorplanning Algorithm (cont’d) Cost function:  Volume  # of storages  Penalty term for fixed-cube constraint

21 Two Methods for Fixed-cube Constraint Guide the tree perturbation based on cube violation probability p w, p h, and p t  p w = k/n, where k is the # of floorplans whose width exceeds the 3D cube in the last n iterations  If p w is large, increase the probability of placing tasks along the Y or T direction Add the excessive length into the cost function Excessive length Max. completion time Fixed architecture An infeasible floorplan

22 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

23 Experimental Settings Implemented our algorithm in C++ language on a 1.2 GHz SUN Blade-2000 machine with 8GB memory Implemented the algorithm of [Su and Chakrabarty, DAC’05] on the same machine Tested two bioassays:  Colorimetric protein assay from [Su and Chakrabarty, DAC’05]  Multiplexed in-virto diagnostics from [Su and Chakrabarty, ICCAD’04] Assigned three different design specifications (fixed- cube constraints) to each bioassay

24 Experimental Result Bioassay Design Spec. [Su et al, DAC’05]T-tree Volume CPU time (seconds) Volume CPU time (seconds) Protein [Su et al, DAC’05] 10x10x4009x10x x10x x10x36010x10x x10x x11x3208x13x x11x23866 Avg In vitro [Su et al, ICCAD’04] 10x10x1009x11x99649x8x666 8x8x1209x9x x7x6812 7x7x1409x10x105926x7x8915 Avg T-tree based algorithm is more efficient and effective Result that cannot satisfy the fixed-cube constraint volume = area × assay completion time

25 Resulting Placement of the Protein Bioassay Volume = 10x10x270 (10x10x400 fixed-cube constraint)

26 Outline Introduction T-tree Based Placement Formulation Floorplanning Algorithm Experimental Result Conclusion

27 Conclusion Formulated the placement problem of biochips as the temporal floorplanning problem First work to apply a topological representation to the placement problem of biochips Demonstrated the effectiveness and efficiency of our algorithm Future work:  Consider fault and defect tolerance during floorplanning

Thank you for your attention

Q & A

30 Question # 1 Q: Why choose the T-tree representation over other 3D representations (3D-subTCG, ST, 3D-slicing tree) ? A: Three reasons:  1. T-tree models the compacted floorplan, thus it has the advantage of volume optimization  2. T-tree is more efficient for large-scale circuits than 3D-subTCG, ST  3. T-tree is more effective in handling the storages T-tree can determine the # of storages and duration of each storage before packing with only O(n) time 3D-subTCG and ST needs O(n^2) time before packing 3D-slicing tree cannot obtain this information before packing It is difficult for 3D-slicing tree to satisfy the storage constraint

31 Question # 2 Q: Why add the # of storages in the cost function? A: Two reasons:  1. Generally, the smaller # of storages, the more compact 3D floorplan we can have  2. Release the volume occupied by storages for reconfigurable task to use

32 Question # 3 Q: Why your algorithm is better than previous work? A: There are two reasons:  1. T-tree is better in volume optimization than previous greedy placement method  2. Smoother optimization process by minimizing volume instead of area plus completion time