1 PreFPIX2 Inner board and test beam triggering Gabriele Chiodini Fermilab - Jan 07, 02

2 We have to add: 3 connectors (instead of existing I/O signals and power lines). 2 LVDS receivers + LVDS 3 transmitters each one is a DS92LV090A chip. Resistors for the receivers. 1 Level translator from 3.3V to 2.5V consisting of a PI74AVC chip. Several jumpers in order to be used for preFPIX2Tb and preFPIX2I. High voltage for the chip. No Ground for the innermost guard ring or pixel side guard ring. Bypass capacitances. We don’t have at the output: addr_5-7 (No jumper for that) core_error (Jumper available) Modification to the layout As now ( not mounted in tb) In power connector I/O connectors The new board doesn’t have components in the backside but the power connector leads

3 Connectors 2 SAMTEC connectors: The same type as mezzanine card LVDS signal pairs each one. Black lines not used. Green lines used. Red lines used for preFPIX2I (small hardware modification on mezzanine card required). 1 MOLEX connector (34-36 pins): LV PS HV PS Currents Charge injection In this way we use one pci card to readout two preFPIX2. A 13 slots pci-bus extender can take not more than 6 PTA+mezzanine cards: 4 PTA+mezz. cards for the telescope (up to 8 FPIX1 planes not daisy chained) 2 PTA+mezz. cards for the devices under test (up to 4 preFPIX2)

4 Board features Size: 6 inches by 6 inches = cm by cm Thickness: inches = 1.57 mm 4 Cu layers (Thickness?): – Top layer is GND + Signals. – Second layer is VDDA. – Third layer is VDDD. – Bottom is GND. Chip position markers. Screw holes near the 4 corners: –¼ of inch from the sides. –1/8 of inch diameter. Thinning: yes (see next slide).

5 Radiation length CuSiG10 X 0 [cm] d/ X 0 d=0.4mm? 2.8%? d=1 mm 1.1% d=1.2 mm 0.6%

6 Cabling and mounting PC board windows for cable feed-throw (compatible with dry nitrogen? Some isolating rubber around?). LV, HV and currents connected to a front panel inside the “hut” (To connect CAEN PS and CPPM modules). I/O signals connected to the mezzanine cards installed on the pci-bus extender in the counting room. Metal support plate

7 Coincidences Upstream and downstream scintillators No further counters (no pin diodes) From each pixel board the Chip_or signal (or equivalent signal) must be available to be put in the trigger The trigger coincidence is formed in the counting room with NIM modules.

8 N BCO Gate Triggering (under discussion) Data reduction. Redundancy. Robustness ( for ex.: BCO not correlated with particles ). Coincidence pulse Pixel hits Coinc. pulse hit with BCO = i. Pixel hits with BCO between [i and i+N]. Mezzanine card Brad has already a very first draft about pixel telescope electronics Calibration readout. Continuous readout. Coincidence readout (see block diagram underneath).