I2C Master Core Simulation Environment. I2C Master Core Requirements Coverage (*) Requirement I2C IP RS-906: The I2C IP shall define the period of time,

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Presentation transcript:

I2C Master Core Simulation Environment

I2C Master Core Requirements Coverage (*) Requirement I2C IP RS-906: The I2C IP shall define the period of time, in which the SDA or SCL lines are not active (except the situation when SDA is low), that will be called timeout situation. This period of time is 20 SCL clock periods. Counting for timeout is performed starting on the current byte of data on the SDA line. (*) Requirement I2C IP RS-907: The I2C IP shall implement internal HW reset to I2C bus signals, when a timeout situation occurs (see I2C IP RS-906). (*) Simulation Procedure for Coverage (example): 1.Initiate read request from i2c slave (slave address = 0x01; sub-address=0x03): 2.Wait for start of the i2c transaction (“sda” falling edge). 3.Wait for nine i2c clocks. 4.Force “low” logic state on “scl” signal. 5.Wait for 20 i2c clock cycles and verify the i2c_interupt signal is at high logic state value. [Covers: I2C IP RS-906] 6.Wait for one main clock cycle and verify the i2c_interupt signal is at low logic state value. [Covers: I2C IP RS-907] 7.Release “scl” signal. 8.Verify that the value of i2c outputs (“scl” and “sda”) is identical to their reset value.

(*) Simulation Procedure for Coverage (example): 1.Initiate read request 2.Wait for start of the i2c transaction (“sda” falling edge). 3.Wait for nine i2c clocks. 4.Force “low” logic state on “scl” signal. 5.Wait for 20 i2c clock cycles and verify the i2c_interupt signal is at high logic state value. 6.Wait for one main clock cycle and verify the i2c_interupt signal is at low logic state value. 7.Release “scl” signal. 8.Verify that the value of i2c outputs (“scl” and “sda”) is identical to their reset value. I2C Master - Simulation Procedure I2C read command Force model I2C Bus I2C Master (DUT) Register bus model Discrete model Wait on signal model 1 2,3 5,6,8 4,7

I2C Master - Simulation Waveform Read command initiation By writing via register bus. I2c_interrupt rises for one clock I2c transaction slave address (0x01) + read command = 0x03 sub-address=0x02