Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Topics Basics of register-transfer design: –data paths and controllers; –ASM charts. Pipelining.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Register-transfer design A register-transfer system is a sequential machine. Register-transfer design is structural— complex combinations of state machines may not be easily described solely by a large state transition graph. Register-transfer design concentrates on functionality, not details of logic design.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Register-transfer system example A register-transfer machine has combinational logic connecting registers: DQ combinational logic DQDQ combinational logic combinational logic

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Block diagrams Block diagrams specify structure: wire bundle of width 5

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Register-transfer simulation Simulates to clock-cycle accuracy. Doesn’t guarantee timing. Important to get proper function of machine before jumping into detailed logic design. (But be sure to take into account critical delays when choosing register- transfer organization.)

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Simulation coding Hardware description languages are typically supported by a simulation system: VHDL, Verilog, etc. –Simulation engine takes care of scheduling events during simulation. Can hand-code a simulation in a programming language. –Must be sure that register-transfer events happen in proper order.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Sample VHDL code sync: process begin wait until CLOCK’event and CLOCK=‘1’; state <= state_next; end process sync; combin: process begin case state is when S0 => out1 <= a + c; state_next <= S1;... end process combin; sync process models registers combin process models combinational logic

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Sample C simulator while (TRUE) { switch (state) { case S0: x = a + b; state = S1; next; case S1:... } loop executed once per clock cycle each case corresponds to a state; sets outputs, next state

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Data path-controller systems One good way to structure a system is as a data path and a controller: –data path executes regular operations (arithmetic, etc.), holds registers with data- oriented state; –controller evaluates irregular functions, sets control signals for data path.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Data and control are equivalent We can rewrite control into data and visa versa: –control: if i1 = ‘0’ then o1 <= a; else o1 <= b; end if; –data: o1 <= ((i1 = ‘0’) and a) or ((i1 = ‘1’) and b); Data/control distinction is useful but not fundamental.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Data operators Arithmetic operations are easy to spot in hardware description languages: –x <= a + b ; Multiplexers are implied by conditionals. Must evaluate entire program to determine which sources of data for registers. Multiplexers also come from sharing adders, etc.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Conditionals and multiplexers if x = ‘0’ then reg1 <= a; else reg1 <= b; end if; code register-transfer

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Alternate data path-controller systems controller data path one controller, one data path controller data path controller data path two communicating data path-controller systems

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf ASM charts An ASM chart is a register-transfer description. ASM charts let us describe function without choosing a partitioning between control and data. Once we have specified the function, we can refine it into a block diagram which partitions data and control.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Sample ASM chart

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf ASM state An ASM state specifies a machine state and a set of actions in that state. All actions occur in parallel. s1 x = a + b y = c - d + e o1 = 1 name of state (notation only)

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Actions in state Actions in a state are unconditionally executed. A state can execute as many actions as you want, but you must eventually supply hardware for all those actions. A register may be assigned to only once in a state (single-assignment rule).

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Implementing operations in an ASM state state with one addition two additions requires two adders

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Sequences of states States are linked by transitions. States are executed sequentially. Each state may take independent actions (including assigning to a variable assigned to in a previous state). s1 x = a + b s2 x = c + d y = a + d

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Data paths from states Maximum amount of hardware in data path is determined by state which executes the most functionality. Function units implementing data operations may be reused across states, but multiplexers will be required to route values to the shared function units.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Function unit sharing example mux allows + to compute a+b, a+c

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Conditionals Conditional chooses which state to execute next based on primary input or present state value. Can be drawn in either of two ways: a = b x T F

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Execution of conditionals An ASM chart describes a Moore sequential machine. If the logic associated with an ASM chart fragment doesn’t correspond to a legal sequential machine, then it isn’t a legal ASM chart. Conditional can evaluate only present state or primary input value on present cycle.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Implementing an ASM branch in a Moore machine ASM chart state transition graph of controller

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Mealy machines and ASM Mealy machine requires a conditional output. ASM notation for conditional output: i1 0 y = c + d

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Extracting data path and controller ASM chart notation helps identify data, control. Once you choose what values and operations go into the data path, you can determine by elimination what goes into the controller. Structure of the ASM chart gives structure of controller state transition graph.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Data path-controller extraction

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipelines Provide higher utilization of logic: Combinational logic

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline metrics Throughput: rate at which new values enter the system. –Initiation interval: time between successive inputs. Latency: delay from input to output. Delay through logic is D, n blocks. L = D. T = n/D. P = D/n.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Clock period and throughput vs. pipeline depth

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Simple pipelines Pure pipelines have no control. Choose latency, throughput. Choose register locations with retiming. Overhead: –Setup, hold times. –Power.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipelining registers

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Bad cutset for pipelining

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Utilization Must fill, drain pipe at start and end of computation. Given D cycles of data, n-stage pipe: –U = D/(D+n)

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Complex pipelines Actions in pipeline depend on data or external events. Data dependencies may be forward or backward. Actions on pipe: –Stall values. –Abort operation. –Bypass values.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline with feedforward constraint

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline with feedback constraint

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline with shared hardware

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline control Controllers are necessary when pipe stages take conditions. Unconditional pipe stage controller has one state, one transition.

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline with distributed control

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Pipeline controller with condition

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Distributed control for pipeline flush

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Control for hardware sharing

Modern VLSI Design 4e: Chapter 8 Copyright  2008 Wayne Wolf Product machine for distributed control Distributed control is hard to verify because state is not centralized. Product machine form identifies global control actions. Can verify using symbolic simulation, model checking.