FLIP FLOP By : Pn Siti Nor Diana Ismail CHAPTER 1

Sequential logic Astable Monostable Bistable - No stable state - 1 stable state - 2 stable states - Use oscillator to - one shot control i. SET generate waveform timing single pulse when ii. RESET trigger - e.g : Flip-flops, latches

An Introduction Latches and Flip-flops (FF) are the basic single-bit memory elements used to build sequential circuit with one or two inputs/outputs, designed using individual logic gates and feedback loops. Latches are bistable devices whose state normally depend on asynchronous input. Edge triggered FFs are bistable devices which synchronous input whose state depend on the input only at trigerring transition of clock pulse.

Latch vs Flip-Flop LatchFlip-flop -Asynchronous bistable devices (Change it state any time depend when its input change) -Synchronous bistable devices (output change state at specific point depend on clock pulse) 3 types : -S-R latch - Gated S-R latch - Gated D latch Edge-trigger FF : -S-R Flip-flop -J-K Flip-flop -D Flip-flop Pulse trigger FF(Master Slave ) The basic difference between Latches & FFs: the way in which they are changed from one state to the another state.

LATCH A type of temporary storage devices. Bistable devices or multivibrator. Asynchronous devices It has 3 types: i.Basic S-R latch, divide by 2 categories : - Active – HIGH input S-R latch - Active – LOW input S-R latch ii.Gated S-R latch iii. Gated D latch

i. S-R latch i. Active – HIGH input S-R latch ii. Form with 2 cross coupled NOR Gated (a)Logic diagram (b)Logic symbol

Truth Table for Active-HIGH input S-R latch SRQQ’Comments 00QQ’ No Change 0101Reset 1010Set 1111 Invalid condition

Active – LOW input S-R latch i. Form with 2 cross coupled NAND Gated (a)Logic diagram (b)Logic symbol

Truth table for Active-LOW input S-R latch S’R'QQ’Comments 11QQ’ No Change 0110Set 1001Reset 0011 Invalid condition

Example : Active – LOW input S-R latch Normally, when Q is HIGH, Q’ is LOW, The output of latch are always compliment each other

Assignment 1 Draw the output waveform for the Active High input SR Latch in diagram below

ii. Gated S-R latch It requires an enable input, EN OPERATION : i.S-R control the state, when EN is high ii.Latch will not change until EN is high iii. When it remains HIGH, output will control by S-R input iv.Invalid state happen when S-R are simultaneously HIGH

Truth table for Gated S-R latch SRG/ENQQ’ 000QQ’hold 100QQ’hold 010QQ’hold 110QQ’hold 001QQ’no change 10110set 01101reset 11100not allowed

Example : Gated S-R latch

iii. Gated D latch Its only has one input The input is called data input (D) OPERATION : i.D is HIGH, EN is HIGH, latch will SET ii.D is LOW, EN is HIGH, latch will RESET The output Q is follow the input D, when EN is HIGH

Truth table for Gated D latch DG/ENQQ’ 00QQ’hold (NC) 10QQ’hold (NC) 0101Reset 1110Set

Example : Gated D latch The output follows the input when the gate is high but is in a hold when the gate is low. ~ En=high ‘1’, Q output will reset/set depend on D input. ~ En=low ‘0’, Q output will hold condition.

Flip-flop (FF) It is a synchronous bi-stable devices. edge-triggered FFs, Pulse Trigger FF (master slave) It has 3 types of edge-triggered FFs, i.J-K ii. S-R iii. D OPERATION: Change state either at positive edge (rising edge) or negative edge (falling edge) of clock pulse, and sensitive to it input only at transition of CLK. +ve edge-triggered has no bubble at input. -ve edge-triggered has bubble at input. to identify edge-triggered FF by check it small triangle inside the block at clock (C) input. (Dynamic indicator)

A clock signal is a periodic square wave that indefinitely switches values from 0 to 1 and 1 to 0 at fixed intervals. Rising edges of the clock (Positive-edge triggered) Falling edges of the clock (Negative-edge triggered) Clock signal Clock Cycle Time 1 0 Clock signals & Synchronous Sequential Circuit

What is +ve and –ve Edge trigger ??

i.Edge trigger S-R Flip-flop Assume positive edge-triggered FF is RESET. The output result Q’ is complement (1’s) of output Q. Logic symbol

Example : S-R Flip-flop

ii.Edge trigger D Flip-flop A +ve edge trigger is form with S-R FF and inverter DCLK/CQQ’_________________ 1 ↑10SET (stores a 1) 0 ↑01 RESET (stores a 0)

Example : D Flip-flop

iii.Edge – trigger J-K Flip-flop  The edge-triggered J-K will only accept the J and K inputs during the active edge of the clock.  The small triangle on the clock input indicates that the device is edge-triggered.  A bubble on the clock input indicates that the device responds to the negative edge. no bubble would indicate a positive edge-triggered device.

Truth table Edge trigger J-K Flip-flop JK CLKQQ’ 00Q 0 Q 0 ’ Hold 0101Reset 1010Set 11Q 0 ’Q 0 Toggle (opposite state)

Example 1: Edge trigger J-K flip flop +ve edge trigger-rising clock pulse

Example 2: Edge trigger J-K flip flop -ve edge trigger – failing clock pulse

Pulse-trigger Flip-flop (Master slave ) It constructed with two latches. The master latch is loaded with the condition of the J-K inputs while the clock is HIGH. When the clock goes LOW, the slave takes on the state of the master and the master is latched. The master-slave is a level-triggered device. The master-slave can interpret unwanted signals on the J-K inputs. *truth table are same with edge trigger except the way it clocked

It composed two section; master and slave Master section : A Gated latch Slave section :A Gated latch with inverted clock and its control by the output of master section Operation: - State is determined by input J-K at leading edge of clock pulse. (in Master section) - It transfer from Master to Slave section at trailing edge of clock pulse because the output of Master is applied to inputs of slave and the clock is inverted

Basic logic diagram for J-K flip-flop

FLIP-FLOP APPLICATIONS 3 general applications of Flip-flop are : i. Parallel Data Storage ii. Frequency Division iii. Counter Application

i.Parallel Data Storage Store data from parallel lines in group of FF.(store data in group) Operation is illustrated in Figure 8. OPERATION : - Using 4 FFs. - 4 parallel data lines is connected to the D input of FFs. - Clock inputs connected together. (triggered by a same clock) - Asynchronous reset inputs connected to a common CLR line. (initially reset all FFs)

Figure 8

ii.Frequency Division Use to reduce the frequency of a periodic waveform Pulse apply to clock input, J-K toggle (J=K=1) Q output is a square wave with one-half the frequency of clock input. Change state each trigger clock. Frequency division,

Example 1 – A single FF J-K FF as a divide-by-2 device. Q is one-half the frequency of CLK. Output change on the +ve clock edge.(this is +ve edge trigger)

Example 2 – Two FFs Using 2 FFs. Q B depends on pulse Q A

iii.Counter -ve edge trigger J-K FF are used(Refer figure in example). Both FF initially RESET FF A toggle when –ve going transition. Q A clocks for Q B FF B toggle when Q A makes HIGH LOW transition

Example Used to generate binary sequence.(00,01,10,11) Two repetition are shown in figure below

Next class Be prepared for next preliminary test : Counter