COMPARISON B/W ELECTRICAL AND OPTICAL COMMUNICATION INSIDE CHIP Irfan Ullah Department of Information and Communication Engineering Myongji university, Yongin, South Korea Copyright © solarlits.com

Computer Bus “Subsystem that transfers data between components inside a computer” First generation Bundles of wire Second generation CPU and memory on one side Third generation HyperTransport “ Lightning Data Transport (LDT)” 25.6 GB/s unidirectional InfiniBand “ Switched fabric communications link” Fibre Channel, PCI Express, Serial ATA (SATA)

Core-to-core Communication Message passing “form of communication used in parallel computing, object-oriented programming, and interprocess communication” Less PCB ~ more data rate ~ less loss Backside Bus “connects the CPU to CPU cache memory” Cache reduces the average time to access memory

Electrical communication inside SOC  Bus topology Shared bus “Masters and slaves connected to a shared bus” Hierarchical bus “Shared buses interconnected by bridges” Ring “Master and slave communicated using a ring interface”  Bus approach AMBA (Advanced Microcontroller Bus Architecture) by ARM Altera by AVALON CORECONNECT by IBM WISHBONE by Silicore Corporation’s VCI (Virtual Component Interface) by VSIA Sinics OCP (Open Core Protocol) by OCP

Cont’d..  Single on-chip bus can not address the needs of all SoCs  Unsuccessful due to Commercial issues Every application needs its own architecture Published in 1985 Published in 2000

Cont’d.. Texas Instruments Ad-hoc approach H.264 digital video decoder For SOC remapping published in 1999

SOC Bus Processing cores on a single chip On-chip interconnection networks are mostly implemented using buses Bus base networks AMBA, Avalon, CoreConnect, STBus, Wishbone, etc... Characteristics using bus Topology Arbitration method bus-width Types of data transfers “The performance of the SoC design heavily depends upon the efficiency of its bus structure”

Used in highly integrated SoC designs Bus agents are on-chip modules PI (Peripheral Interconnect) bus

Interconnects IP cores to on-chip bus OCP (Open Core Protocol)

SOC Bus

Optical fiber communication application

Fastest system

Today A few large cores on each chip Diminishing returns prevent cores from getting more complex Only option for future scaling is to add more cores p switch m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m BUS p p c c L2 Cache Tomorrow Simple cores are more power and area efficient Global structures do not scale; all resources must be distributed Multi-core

Scalability How do we turn additional cores into additional performance? Must accelerate single apps, not just run more apps in parallel Efficient core-to-core communication is crucial Architectures that grow easily with each new technology generation Programming Traditional parallel programming techniques are hard Parallel machines were rare and used only by rocket scientists Multicores are ubiquitous and must be programmable by anyone Power Already a first-order design constraint More cores and more communication  more power Previous tricks (e.g. lower Vdd) are running out of steam Cont’d..

Single shared resource Uniform communication cost Communication through memory Doesn’t scale to many cores due to contention and long wires Scalable up to about 8 cores BUS p p c c L2 Cache DRAM Bus-based Interconnect Electrical communication based cores

Point-to-Point Mesh Network p switch m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m More energy efficient than bus Scalable to hundreds of cores DRAM

Programming Meshes and small cores solve the physical scaling challenge, but programming remains a barrier Parallelizing applications to thousands of cores is hard For high performance, communication and locality must be managed Observations: A cheap broadcast communication mechanism can make programming easier On-chip optical components enable cheap, energy-efficient broadcast

Optical connection 18 p switch m p m p m p m p m p m p m p m p m p m p m p m p m p m p m p m Optical Broadcast WDM Interconnect Electrical Mesh Interconnect

Cont’d.. optical waveguide Signal through every core Signal reaches all cores in <2ns

Cont’d.. 20 N cores

Cont’d.. 21 sending core receiving core flip-flop filter photodetector modulator driver data waveguide transimpedance amplifier multi-wavelength source waveguide  Each core sends data using a different wavelength  no contention  Data is sent once, any or all cores can receive it  efficient broadcast

Cont’d.. sending core A receiving core sending core B FIFO 32 Processor Core FIFO 32 Processor Core FIFO Processor Core 32  Each core contains receive filters and a FIFO buffer for every sender  Data is buffered at receiver until needed by the processing core  Receiver can screen data by sender (i.e. wavelength) or message type

Cont’d..  64 cores, 32 lines, 1 Gb/s  Transmit BW: 64 cores x 1 Gb/s x 32 lines = 2 Tb/s  Receive-Weighted BW: 2 Tb/s * 63 receivers = 126 Tb/s

Mechanism

Research by INTEL 50Gbps Silicon Photonics link

Cont’d..

50Gbps Silicon Photonics link

IBM Research

Cont’d..

IBM optical communication inside chip Links~100 k Length~1 cm BW~1 Tbps Power<10mW

Cont’d.. CMOS-Integrated optical nanophotonics Intra-chip optical network (ICON) “Transmission of data using pulses of light instead of electrical signals” Electrical and optical devices on the same piece of silicon Smaller, faster and more power-efficient chips Silicon nanophotonics WDM Light sources Modulators Switches Detectors

Cont’d.. Links~100 k Length~ cm BW~1 Tbps Power<1mW

Optical network for 64-core

Cont’d..