Placement

Physical Design Cycle Partitioning Placement/ Floorplanning Placement/ Floorplanning Routing Break the circuit up into smaller segments Place the segments on the chip Layout the wire paths 2

Floorplanning and Placement Partitioning:  Circuit divided into smaller modules Floorplanning:  Block outlines are determined Pin Assignment:  Pin locations are determined  Placement  to determine the locations of standard cells or logic elements within each block Objectives:  Total wire length  Performance  … 3

Placement Steps Global placement:  Assigns general locations to movable objects Detailed placement:  Incrementally improves object locations −e.g., swapping cells Legalization:  Before or during detailed placement: −Align cells with rows and columns −Remove overlaps −Should minimize displacement from global placement locations −Minimize impacts on interconnect length and circuit delay 4

5 Placement Stages Global Placement Detailed Placement

Placement Stages Run time:  Of the same order Memory:  Global placement requires much more Parallelism:  Global placement is difficult to parallelize Performance-driven:  More accurate delay information in detailed placement 6

7 Optimization Objectives Total Wirelength Wire Congestion Signal Delay © 2011 Springer Verlag

Consequences of Placement 8

A bad placement A good placement 9

Placement Considerations  Module Shapes:  Rectangular (Possibly Rectilinear)  Aspect Ratio: H/W (constrained)  L-Shape (complex)  Routing Considerations:  Routability  Routing Area Estimation 10

Placement Considerations  High Performance Design:  Critical Nets.  Pre-placed Modules:  E.g. Clock buffer in the middle. 11

Routing Length Estimation Interconnects:  Unknown during placement  Estimate Two-terminal nets:  Euclidean distance  Manhattan distance (rectilinear distance)  Octilinear distance 12

13 Wirelength estimation for a net Objectives: Total Wirelength Half- perimeter wirelength (HPWL) HPWL = Complete graph (clique) Clique Length = (2/p)  e  clique d M (e) = 14.5 Monotone chain Chain Length = Star model Star Length = Sait, S. M., Youssef, H.: VLSI Physical Design Automation, World Scientific

Objectives: Total Worelength Star:  One pin as the source  Useful for timing optimization  Uses only p-1 edges −  advantageous for high pin count nets  Overestimates wirelength 14

Objectives: Total Wirelength Complete graph (clique):  p pins −  No. of edges: 15  Spanning tree: −  No. of edges: p – 1  Normalization factor: p/2

16 Sait, S. M., Youssef, H.: VLSI Physical Design Automation, World Scientific Objectives: Total Wirelength Rectilinear minimum spanning tree (RMST) RMST Length = Rectilinear Steiner minimum tree (RSMT) RSMT Length = Rectilinear Steiner arborescence model (RSA) RSA Length = Single- trunk Steiner tree (STST) STST Length = Wirelength estimation for a net (cont’d)

Objectives: Total Wirelength RSA:  One pin as the source: s 0  Path length from s 0 to any s i must be equal to s 0 ~ s i Manhattan distance  Minimum length RSA: NP-hard STST:  Easy to construct  Commonly used for estimation 17

18 Preferred method: Half-perimeter wirelength (HPWL)  Fast (order of magnitude faster than RSMT)  RSMT: NP-hard  = RSMT for 2- and 3-pin nets (70%-80% of nets in most modern designs)  Margin of error for real circuits approx. 8% [Chu, ICCAD 04] Objectives: Total Wirelength RSMT Length = HPWL = w h

19 Objectives: Total Wirelength Total wirelength with net weights (weighted wirelength) For a placement P  estimated total weighted wirelength: a b d c f e b1b1 e1e1 c1c1 a1a1 d1d1 d2d2 f2f2 f1f1 NetsWeights N 1 = (a 1, b 1, d 2 )w(N 1 ) = 2 N 2 = (c 1, d 1, f 1 )w(N 2 ) = 4 N 3 = (e 1, f 2 )w(N 3 ) = 1 w(net): weight of net L(net): estimated wirelength of net Example:

Objectives: Congestion Two choices:  Channel-based  Channel segment-based Channel Segment 20

Cost Function Using Channel For each channel i w i : total number of nets whose bounding rectangles intersect with channel i: w 1 =0 w 2 =2 w 3 =1 w 4 =1 w 5 =1 w 6 =0 Net-Crossing Histogram 21

 Assign a threshold value t i on the wiring capacity for each channel i. −Cost function = Total wire length +   i (max{w i -t i, 0}) 2 Cost Function Using Channel 22

Cost Function Using Channel Segment For each net j,  R j : bounding rectangle  p j : half perimeter of R j  l j : number of channel segments that intersected or enclosed by R j. Expected occupancy of net j in each segments  p j / l j w i of a segment i =  sum of all the expected occupancy in i 23

Cost Function Using Channel Segment Cost function = Total wirelength +   i (max{w i -t i, 0}) 2 Expected Occupancy = 2/4 Expected Occupancy = 3/7 w i = 2/4+3/7 24

Objectives: Delay Delay:  Static timing analysis: −For each path p, if delay(p) > timing budget (p)  Timing is violated - details: later 25

Placement Problem Formulation Blocks: B 1, …, B n B i :(w i, h i ) Nets: N 1, …, N m Net Length Estimation for N i : L i Rectangular Spaces for Routing: Q 1, …, Q k 26

Placement Problem Formulation NP-Complete Problem Find the position and orientation of all B i ’s such that: 27

Macrocell Placement Different Block Sizes and Shapes. Primary Objective Function: Area.  The main cause of area waste: non-regularity. Opposite to Connection Length Objective? 28

Standard-Cell Placement Equal Height Cells  Easier Placement in Rows. Area Minimization:  Minimize Total Height  Minimize Widest Width  (Balance in Row Widths) 29

Gate Array Placement Mapping Components to Gates.  Inputs: −A set of blocks: {B 1, …, B n }, −A set of slots: {S 1, …, S r } (r >= n)  Objective: −Map B i ’s to S j ’s such that no two blocks map onto one slot −And the result is routable. e.g. FPGA. Customized WiringPrefabricated gates 30

Placement Algorithms Classification Constructive Iterative Improvement Global Placement Algorithms 31

Placement Algorithms Classification Deterministic Stochastic Global Placement Algorithms 32

Placement Algorithms Classification Simulation- Based Analytical Global Placement Algorithms Partitioning -Based …. 33

Placement Algorithms Classification Simulation- Based 34 Simulated annealing Simulated evolution Force-directed Neural networks ….

Placement Algorithms Classification Partitioning -Based 35 Breuer Min-cut Terminal propagation Dragon (UCLA) Capo (Michigan) ….

Placement Algorithms Classification Analytical 36 Quadratic placement ILP-based ….