SEQUENTIAL CIRCUITS Component Design and Use

Register with Parallel Load  Register: Group of Flip-Flops  Ex: D Flip-Flops  Holds a Word of Data  Loads in Parallel on Clock Transition  Asynchronous Clear (Reset)

Register with Load Control  Load Control = 1  New data loaded on next positive clock edge  Load Control = 0  Old data reloaded on next positive clock edge

Shift Registers  Cascade chain of Flip-Flops  Bits travel on Clock edges  Serial in – Serial out, can also have parallel load / read

Parallel Data Transfer °All data transfers on rising clock edge °Data clocked into register Y

Parallel versus Serial  Serial communications is defined as  Provides a binary number as a sequence of binary digits, one after another, through one data line.  Parallel communications  Provides a binary number through multiple data lines at the same time.

parallel inputs parallel outputs serial transmission Shift register application  Parallel-to-serial conversion for serial transmission

Serial Transfer  Data transfer one bit at a time  Data loopback for register A Time T0 T1 T2 T3 T4 Reg A Reg B

Serial Transfer of Data  Transfer from register X to register Y (negative clock edges for this example)

DQDQDQDQ IN OUT1OUT2OUT3OUT4 CLK OUT Pattern recognizer  Combinational function of input samples  in this case, recognizing the pattern 1001 on the single input signal IN OUT1 OUT2 OUT3 OUT4 OUT

Serial Addition (D Flip-Flop)  Slower than parallel  Low cost  Share fast hardware on slow data

Serial Addition (D Flip-Flop)  Only one full adder  Reused for each bit  Start with low-order bit addition  Note that carry (Q) is saved  Add multiple values.  New values placed in shift register B

Serial Addition (D Flip-Flop)  Shift control used to stop addition  Generally not a good idea to gate the clock  Shift register can be of arbitrary length  FA is built from combin. logic

Universal Shift Register  Clear  Clock  Shift  Right  Left  Load  Read  Control

Counters  Counter: A register that goes through a prescribed series of states  Binary counter  Counter that follows a binary sequence  N bit binary counter counts in binary from n to 2 n-1  Ripple counters triggered by initial Count signal  Applications:  Watches  Clocks  Alarms  Web browser refresh

Binary Ripple Counter  Reset signal sets all outputs to 0  Count signal toggles output of low- order flip flop  Low-order flip flop provides trigger for adjacent flip flop  Not all flops change value simultaneously  Lower-order flops change first  Focus on D flip flop implementation

Another Asynchronous Ripple Counter °Similar to T flop example on previous slide

Asynchronous Counters  Each FF output drives the CLK input of the next FF.  FFs do not change states in exact synchronism with the applied clock pulses.  There is delay between the responses of successive FFs.  Ripple counter due to the way the FFs respond one after another in a kind of rippling effect. A3A3 A2A A1A A0A

Synchronous counters  Synchronous(parallel) counters  All of the FFs are triggered simultaneously by the clock input pulses.  All FFs change at same time  Remember  If J=K=0, flop maintains value  If J=K=1, flop toggles  Most counters are synchronous in computer systems.  Can also be made from D flops  Value increments on positive edge  Note that low-order bit (A 0 ) toggles on each clock cycle

Synchronous UP/Down counters  Up/Down Counter can either count up or down on each clock cycle  Up counter counts from 0000 to 1111 and then changes back to 0000  Down counter counts from 1111 to 0000 and then back to 1111  Counter counts up or down each clock cycle  Output changes occur on clock rising edge

Counters with Parallel Load  Counters with parallel load can have a preset value  Load signal indicates that data (I 3 …I 0 ) should be loaded into the counter  Clear resets counter to all zeros  Carry output could be used for higher-order bits

Counters with Parallel Load Clear Clk Load Count Function 0 X X X Clear to 0 1 ↑ 1 X Load inputs 1 ↑ 0 1 Count 1 ↑ 0 0 No Change Function Table  If Clear is asserted (0), the counter is cleared  If Load is asserted data inputs are loaded  If Count asserted counter value is incremented

Binary Counter with Parallel Load and Preset Presettable parallel counter with asynchronous preset. If PL’ = 0, load P into flops

Binary Counter with Parallel Load and Preset Commercial version of binary counter

MEMORY  Memory is a collection of storage cells with associated input and output circuitry  Possible to read and write cells  Random access memory (RAM) contains words of information  Data accessed using a sequence of signals  Leads to timing waveforms  Decoders are an important part of memories  Selects specific data in the RAM  Static RAM loses values when circuit power is removed.

Preliminaries  RAMs contain a collection of data bytes  A collection of bytes is called a word  A sixteen bit word contains two bytes  Capacity of RAM device is usually described in bytes (e.g. 16 MB)  Write operations write data to specific words  Read operations read data from specific words  Note: new notation for OR gate

RAM Interface Signals  Data input and output lines carry data  Memory contains 2 k words  k address lines select one word out of 2 k  Read asserted when data to be transferred to output  Write asserted when data input to be stored

Preliminaries  Memory – big array of data  Each address refers to one word/byte of data  You can read or write the data

Random Access Memory Fundamentals  Lets consider a simple RAM chip  8 words of 2 bytes each (each word is 16 bits)  How many address bits do we need? word Pick one of 8 locations Dec Binary Data and Input signals ____ address signals Each bit stored in a binary cell

RAM Size °If memory has 2 k words, k address bits are needed °2 3 words, 3 address bits °Address locations are labelled 0 to 2 k -1 °Common subscripts: °Kilo – 2 10 °Mega – 2 20 °Giga

Write Operation 1. Apply binary address of word to address lines 2. Apply data bits to data input lines 3. Activate write input Data output lines unused Read input signal should be inactive Delay associated with write

Read Operation 1. Apply binary address of word to address lines 2. Activate read input Data input lines unused Write input signal should be inactive Delay associated with read Memory enable used to allow read and writes

Memory Timing – write operation  Memory does not use a clock  Control signals may be generated on clock edges  Cycle time – time needed to write to memory  If cycle time is 50 ns, 3 clock edges required (T1, T2, T3)

 Access time indicates time to read  Address indicates location  Data valid on Data Output following access time Timing Waveforms – read operation Multiple clock signals needed for data read in this example * Note ordering of signals (address, mem enable)

Comments about Memory Access and Timing  Most computers have a central processing unit (CPU)  Processor generates control signals, address, and data  Values stored and then read from RAM °The timing of the system is very important. Processor provides data for the cycle time on writes Processor waits for the access time for reads

Types of Random Access Memories  Static random access memory (SRAM)  Operates like a collection of latches  Once value is written, it is guaranteed to remain in the memory as long as power is applied  Generally expensive  Used inside processors (like the Pentium)  Dynamic random access memory (DRAM)  Generally, simpler internal design than SRAM  Requires data to be rewritten (refreshed), otherwise data is lost  Often hold larger amount of data than SRAM  Longer access times than SRAM  Used as main memory in computer systems

Inside the RAM Device  Address inputs go into decoder  Only one output active  Word line selects a row of bits (word)  Data passes through OR gate  Each binary cell (BC) stores one bit  Input data stored if Read/Write is 0  Output data driven if Read/Write is 1

38 Connecting three-state buffers together  You can connect several three- state buffer outputs together if you can guarantee that only one of them is enabled at any time.  Allows us to save some wire and gate costs.

Inside the SRAM Device  Basis of each SRAM cell is an S-R latch  Note that data goes to both S and R  Select enables operation  Read/write enables read or write, but not both

Inside the SRAM Device  Note: delay primarily depends on the number of words  Delay not effected by size of words °How many address bits would I need for 16 words? Word

Inside the SRAM Device

Read/ Word select Read/Write logic Data in Data out Write Bit select (b) Block diagram RAM cell RAM cell RAM cell Data input Chip select Read/Write Data output A 3 A 2 A 1 A to-16 Decoder A 3 A 2 A 1 A 0 Data input Data output (a) Symbol Read/ Write Memory enable 16 x 1 RAM

Making a larger memory  We can put four 64K x 8 chips together to make a 256K x 8 memory.

Two-dimensional decoding

Data input Read/Write XXX A 1 A 0 RAM cell Read/Write logic Data in Data out Read/ Write Bit select RAM cell Read/Write logic Data in Data out Read/ Write Bit select RAM cell RAM cell 14 Read/Write logic Data in Data out Read/ Write Bit select RAM cell RAM cell 15 Read/Write logic Data in Data out Read/ Write Bit select Column decoder 2-to-4 Decoder with enable Column select 2 Enable 3 Chip select Data output Row select Row decoder A 2 A 3 X 2-to-4 Decoder

Address Multiplexing