June 3, 2005H Themann SUSB Physics & Astronomy 1 Phenix Silicon Pixel FEM S. Abeytunge C. Pancake E. Shafto H. Themann.

Slides:



Advertisements
Similar presentations
Pixel Chip Testing S. Easo, RAL Current Status of the Pixel Chip Testing. Plans for an LHCb Test Setup at CERN.
Advertisements

M.J. LeVine1STAR HFT meeting, Sept 27-28, 2011 STAR SSD readout upgrade M. LeVine, R. Scheetz -- BNL Ch. Renard, S. Bouvier -- Subatech J. Thomas -- LBNL.
Better Debugging of Embedded via a Debug Port ECE152.
Alice EMCAL Meeting, July 2nd EMCAL global trigger status: STU design progress Olivier BOURRION LPSC, Grenoble.
1 Performed By: Khaskin Luba Einhorn Raziel Einhorn Raziel Instructor: Rivkin Ina Spring 2004 Spring 2004 Virtex II-Pro Dynamical Test Application Part.
Better Debugging of Embedded via a Debug Port ECE152.
Slide 1 FEC Software 21 April 2004 R.Stone Rutgers University Pixel FEC Workshop.
HCAL FIT 2002 HCAL Data Concentrator Status Report Gueorgui Antchev, Eric Hazen, Jim Rohlf, Shouxiang Wu Boston University.
Peter Chochula CERN-ALICE / Dpt. Of Nucl. Physics MFF UK Bratislava Queued... HTTP IPX,SPX Component Client Component Client COM Component Client COM DCE-RPC.
The 6713 DSP Starter Kit (DSK) is a low-cost platform which lets customers evaluate and develop applications for the Texas Instruments C67X DSP family.
Institute of Experimental and Applied Physics Czech Technical University in Prague 11th December 2007 Michal Platkevič RUIN Rapid Universal INterface for.
® ChipScope ILA TM Xilinx and Agilent Technologies.
Mathieu Goffe EUDET JRA1 meeting, DESY Wednesday 30 January 2008 IPHC, 23 rue du Loess BP 28, 67037, Strasbourg Cedex 02, France.
1 States report for readout system 1.PHENIX readout system overview 2.High speed data link 3.Digital pilot ASIC 4.Schedule Hiroyuki
In-Beam PET Status Report -- TPS. 2 TPS project PET monitoring prototype 2D view of the FOV coverage of the 4+4 modules Use of 4 modules vs. 4 modules.
Normal text - click to edit RCU – DCS system in ALICE RCU design, prototyping and test results (TPC & PHOS) Johan Alme.
Leo Greiner IPHC testing Sensor and infrastructure testing at LBL. Capabilities and Plan.
Columbia University IN THE CITY OF NEW YORK Environmental Monitoring DOE Review June 2-3, 2009.
Tuesday September Cambridge1 GDCC “next replacement of the LDA” Franck GASTALDI.
14 Sep 2005DAQ - Paul Dauncey1 Tech Board: DAQ/Online Status Paul Dauncey Imperial College London.
U N C L A S S I F I E D FVTX Detector Readout Concept S. Butsyk For LANL P-25 group.
PHENIX upgrade DAQ Status/ HBD FEM experience (so far) The thoughts on the PHENIX DAQ upgrade –Slow download HBD test experience so far –GTM –FEM readout.
M. Lo Vetere 1,2, S. Minutoli 1, E. Robutti 1 1 I.N.F.N Genova, via Dodecaneso, GENOVA (Italy); 2 University of GENOVA (Italy) The TOTEM T1.
Online Calibration of the D0 Vertex Detector Initialization Procedure and Database Usage Harald Fox D0 Experiment Northwestern University.
Pixel hybrid status & issues Outline Pixel hybrid overview ALICE1 readout chip Readout options at PHENIX Other issues Plans and activities K. Tanida (RIKEN)
Frontend of PHENIX Si pixel K. Tanida (RIKEN) FEM/DAQ meeting for PHENIX upgrade (10/24/02) Outline Overview of PHENIX Si pixel detector ALICE1 chip readout.
Yuri Velikzhanin NuTel TV meeting, June 13 (Friday), 2003 Status of electronics for NuTel prototype.
HBD FEM the block diagram preamp – FEM cable Status Stuffs need to be decided….
Update on the HBD Craig Woody BNL DC Meeting June 8, 2005.
Global Trigger H. Bergauer, Ch. Deldicque, J. Erö, K. Kastner, S. Kostner, A. Nentchev, B. Neuherz, N. Neumeister, M. Padrta, P. Porth, H. Rohringer, H.
Bernardo Mota (CERN PH/ED) 17/05/04ALICE TPC Meeting Progress on the RCU Prototyping Bernardo Mota CERN PH/ED Overview Architecture Trigger and Clock Distribution.
Parallel Data Acquisition Systems for a Compton Camera
Status and planning of the CMX Wojtek Fedorko for the MSU group TDAQ Week, CERN April , 2012.
Instrumentation DepartmentCCLRC Rutherford Appleton Laboratory28 March 2003 FED Project Plan 2003 FED Project aiming to satisfy 2 demands/timescales: Module.
J. Prast, G. Vouters, Arlington, March 2010 DHCAL DIF Status Julie Prast, Guillaume Vouters 1. Future CCC Use in DHCAL Setup 2. Calice DAQ Firmware Implementation.
Xiangming Sun1PXL Sensor and RDO review – 06/23/2010 STAR XIANGMING SUN LAWRENCE BERKELEY NATIONAL LAB Firmware and Software Architecture for PIXEL L.
FVTX Electronics (WBS 1.5.2, 1.5.3) Sergey Butsyk University of New Mexico Sergey Butsyk DOE FVTX review
Test Setup for FE-I3 single chips / modules, FE-I4_proto1 and for full scale FE-I4 Marlon Barbero, Bonn.
NA62 straw tracker readout status Georgios Konstantinou
1 07/10/07 Forward Vertex Detector Technical Design – Electronics DAQ Readout electronics split into two parts – Near the detector (ROC) – Compresses and.
IPHC - DRS Gilles CLAUS 04/04/20061/20 EUDET JRA1 Meeting, April 2006 MAPS Test & DAQ Strasbourg OUTLINE Summary of MimoStar 2 Workshop CCMOS DAQ Status.
Sept. 7, 2004Silicon VTX Workshop - Brookhaven National Laboratory, Long Island, New York Prototype Design of the Front End Module (FEM) for the Silicon.
DEPARTEMENT DE PHYSIQUE NUCLEAIRE ET CORPUSCULAIRE JRA1 - Data Acquisition Status Report Daniel Haas DPNC Genève Extended SC Meeting 1 Sep 2008.
Sensor testing and validation plans for Phase-1 and Ultimate IPHC_HFT 06/15/ LG1.
CF 16/Feb/20031 H8 Beam Test in 2003 ─ Preparation status TGC-Japan electronics group.
1 The TrackFinder GUI D. Acosta, L. Gray, N. Park, H. Stöck University of Florida.
FVTX Electronics (WBS 1.5.2, 1.5.3) Sergey Butsyk University of New Mexico Sergey Butsyk DOE FVTX review
Connector Differential Receiver 8 Channels 65 MHz 12 bits ADC FPGA Receive/buffer ADC data Format triggered Events Generate L1 Primitives Receive timing.
26/11/02CROP meeting-Nicolas Dumont Dayot 1 CROP (Crate Read Out Processor)  Specifications.  Topology.  Error detection-correction.  Treatment (ECAL/HCAL.
JRA-1 Meeting, Jan 25th 2007 A. Cotta Ramusino, INFN Ferrara 1 EUDRB: A VME-64x based DAQ card for MAPS sensors. STATUS REPORT.
1 SysCore for N-XYTER Status Report Talk by Dirk Gottschalk Kirchhoff Institut für Physik Universität Heidelberg.
1 Test Setups for the FE-I4 Integrated Circuit Stewart Koppell 8/1/2010.
STAR Pixel Detector readout prototyping status. LBNL-IPHC-06/ LG22 Talk Outline Quick review of requirements and system design Status at last meeting.
Pixel Atsushi Taketani RIKEN RIKEN Brookhaven Research Center 1.Overview of Pixel subsystem 2.Test beam 3.Each Components 4.Schedule 5.Summary.
October Test Beam DAQ. Framework sketch Only DAQs subprograms works during spills Each subprogram produces an output each spill Each dependant subprogram.
.1PXL READOUT STAR PXL READOUT requirement and one solution Xiangming Sun.
Atsushi Taketani 2005/06/03 VTX meeting 1 PIXEL BUS status 1.Circuit design 2.Design rule and design 3.Schedule.
Rutherford Appleton Laboratory September 1999Fifth Workshop on Electronics for LHC Presented by S. Quinton.
Electronics Status New DCM daughter card works. –Three cards has been assembled. –One daughter card has been send to Jamie yesterday by FedEx overnight.
DHH Status Igor Konorov TUM, Physics Department, E18 PXD DAQ workshop Münzenberg –June 9-10, 2011.
Scalable Readout System Data Acquisition using LabVIEW Riccardo de Asmundis INFN Napoli [Certified LabVIEW Developer]
April 2006 CD1 Review NOvA DAQ 642, hits/sec avg. 20,088 Front-End Boards (~ 3 MByte/sec data rate per FEB) 324 Data Combiner Modules,
ECAL electronics schedule JFMAMJJASONDJFMAM Prototype 2 boards Design Layout Fabrication and assembly Testing, including VFE prototype tests Production.
E. Hazen1 MicroTCA for HCAL and CMS Review / Status E. Hazen - Boston University for the CMS Collaboration.
The Data Handling Hybrid
The Jülich Digital Readout System for PANDA Developments
Production Firmware - status Components TOTFED - status
Sheng-Li Liu, James Pinfold. University of Alberta
PHENIX forward trigger review
Multi Chip Module (MCM) The ALICE Silicon Pixel Detector (SPD)
Presentation transcript:

June 3, 2005H Themann SUSB Physics & Astronomy 1 Phenix Silicon Pixel FEM S. Abeytunge C. Pancake E. Shafto H. Themann

June 3, 2005H Themann SUSB Physics & Astronomy 2 Main Tasks USB - PC Test Interface Na60 Pilot Board Tests Prototype FEM (1.6Gbits/s fast ethernet) FEM –(3-4 channel VME version) –(Production version)

June 3, 2005H Themann SUSB Physics & Astronomy 3 Current Status: Prototype USB interface built and tested Basic FPGA communication code complete Clock and Serial Commands tested with Na60 Pilot Visual Basic code ongoing development USB PC Test Interface: º No special hardware required º Visual Basic executable runs on Windows PC º Execute all Digital Pilot commands º Test and configure Pixel Chips via JTAG º Read FEM status registers º Buffered Pixel data and TDO data

June 3, 2005H Themann SUSB Physics & Astronomy 4 Visual Basic Control Panel

June 3, 2005H Themann SUSB Physics & Astronomy 5 Na60 Pilot Board Tests: º Use Pilot/Pixel test board for FEM development º Develop FPGA Code º Integrate USB test port Current Status: Basic FPGA communication code complete Clock and Serial Commands tested with Na60 Pilot Create JTAG configuration strings Readout Pixel data with Phenix DAQ (GTM, DCM)

June 3, 2005H Themann SUSB Physics & Astronomy 6 Prototype FEM (1.6Gbits/s fast ethernet): º Develop FPGA code for 1.6Gbits/s fast ethernet º “Fast Or” Trigger extraction º Interface with RIKEN Pilot data format º Interface with SPIRO Schedule: Design / LayoutStartJun.22,2005 FabricationSep.12,2005 Test / DebugOct.5, 2005 Interface with SPIROOct.17,2005

June 3, 2005H Themann SUSB Physics & Astronomy 7 FEM (3-4 channel VME version): º Interface to “new” Phenix DAQ ! º Interface to “new” Phenix slow control ! º Develop “Fast Or” trigger module Schedule: Design / Layout StartAug.1 st, 2005 FabricationFeb.2006 Test / DebugMarch2006

June 3, 2005H Themann SUSB Physics & Astronomy 8 FEM (Production version): º FEM º VME trigger module Schedule: Design / LayoutStart Mar. 1 st,2006 FabricationAug.2006 Test / DebugSept.2006

June 3, 2005H Themann SUSB Physics & Astronomy 9 Data Generator - FEM Interface Board

June 3, 2005H Themann SUSB Physics & Astronomy 10 USB Interface Na60 Pilot Board Interface FEM Test Interface Board

June 3, 2005H Themann SUSB Physics & Astronomy 11 Schedule 2005 M J J A S O N D USB Test Interface Design FPGA code VB interface Na60 Pilot Board tests Board arrives at SB Interface to Pilot Readout via Phenix DAQ Prototype FEM (1.6Gbits/s) Design / Layout Fabrication Test / Debug Interface with SPIRO FEM (3-4 channel VME) Design / Layout

June 3, 2005H Themann SUSB Physics & Astronomy 12 Schedule 2006 J F M A M J J A S O FEM (3-4 channel VME) Design / Layout Fabrication Test / Debug VTM (VME Trigger Module) Design / Layout Fabrication Test / Debug FEM (VME Production Ver.) Design / Layout Fabrication Test / Debug