CASE STUDY OF A MULTYCYCLE DATAPATH

Alternative Multiple Cycle Datapath (In Textbook) Minimizes Hardware: 1 memory, 1 ALU Ideal Memory Din Address 32 Dout MemWr 32 ALU 32 ALUOp ALU Control 32 IRWr Instruction Reg 32 Reg File Ra Rw busW Rb busA 32 busB RegWr Rs Rt Mux 0 1 Rt Rd PCWr ALUSrcA Mux 01 RegDst Mux PC MemtoReg Extend Mux Imm 32 ALUSrcB Mux Zero PCWrCondPCSrc 32 IorD Mem Data Reg ALU Out B A << 2 MemRd PC

State Diagram: operations for Each Cycle R-Type IR  Mem[PC] State= A  R[rs] B  R[rt] PC  PC + 4 State= ALUout  A Op B State= R[rd]  ALUout State= Go Next state= Logic Immediate IR  Mem[PC] State= A  R[rs] B  R[rt] PC  PC + 4 State= ALUout  A Op ZeroExt[imm16] State= R[rt]  ALUout State= Go Next state= Load IR  Mem[PC] State= A  R[rs] B  R[rt] PC  PC + 4 State= ALUout  A Op SignExt[imm16] State= MDR  ALUout State= R[rt]  MDR State= Go Next state= Store IR  Mem[PC] State= A  R[rs] B  R[rt] PC  PC + 4 State= ALUout  A Op SignExt[imm16] State= Mem[R]  ALUout State= Go Next state= Cond-Branch IR  Mem[PC] State= A  R[rs], B  R[rt], Z[R[rs]-R[rt]] PC  PC + 4 State= PC  (PC + 4) + (Z=1) (SignExt(imm16) x4) State= Go Next state= IF ID EX/M WB Branch IR  Mem[PC] State=00000 PC  [PC + 4] 28-31, (IMM-26) 26 ] State= Go Next State 00000

Current Op fieldZNext IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W MM-R Wr Dst R I LW SW BEQ IF ID

Current Op fieldZNext IR PC Ops Exec Mem Write-Back State A B Ex Sr ALU S R W MM-R Wr Dst 00000XXXX? R-typex I-typex LWx SWx BEQ x Jumpx xxxxxxx xxxxxxx fun xxxxxxx xxxxxxx or xxxxxxx xxxxxxx add xxxxxxx xxxxxxx xxxxxxx add xxxxxxx R I LW SW BEQ IF ID