1. { CPU Design-Project CPU Design-Project Multicycle Datapath with Finite State Machine as Control Unit N.S.V Ravi Tej Uppu

2. NameMnemicFormat OperationOpcode Add add RR[rd] = R[rs] + R[rt] 0000 And and RR[rd] = R[rs] & R[rt] 0001 Or or RR[rd] = R[rs] | R[rt] 0010 Subtract sub RR[rd] = R[rs] - R[rt] 0011 Not not RR[rd] = nt[ R[rs] | $0] 0100 Xor xor RR[rd] = R[rs] xor R[rt] 0101 Load word lw IR[rt]=M(R[rs]+signExtImm) 0110 Store word sw IM(R[rs]+signExtImm)=R[rt] 0111 Add Imm addi IR[rt] = R[rs] + signExtImm 1000 And Imm andi IR[rt] = R[rs] & signExtImm 1001 Or Imm ori IR[rt] = R[rs] | signExtImm 1010 Branch on equal beq Iif R[rs]==R[rt],PC=PC+4+brn add 1011 Halt hlt JPC = PC - 1 1100 Jump j JPC = jump address 1101 Set on less than slt RR[rd] = (R[rs]<R[rt]) ? 1 : 0 1110 Jump and link jal IR[15]=PC+4; PC = jump address 1111 Core Instruction set:-

3. 15 opcode 1211 rs 87 rt 43 rd 0 Basic Instruction Formats: R 15 opcode 1211 rs 87 rt 43 immediate 0 I J15 opcode 1211 address 0 Name Number Use $zero 0the constant value ‘0’ $at 1assembler Temporary $v0 2values for function results $a0-$a3 3-6arguments $t0-$t3 7-10temporary registers $s0-$s3 11-14saved temporary $ra 15return address Register Name, Number, Use:

4. Multicycle Datapath with Control unit: PC 1 mux 0 Address Memory Mem data Write data Inst(15-12) Instruction( 11-8) Instruction( 7-4) (Inst Reg) Instruction( 4-0) Memory Data Register 1 mux 0 Sign Exten d Read reg 1 read data 1 Read reg 2 Reg-file Write reg read data 2 Write data A B 1 mux 0 3 2 1 0 AL U- op o/p’s Contr ol Op(3- 0) 2 1 0 1 rsrs rt PCWriteCond PCWrite IorD Mem Write IRWrite Regdst RegWrite ALUSrcA ALUSrcB ALUop PCSource zero Inst(0-11) & PC(12-15) rd MemtoReg

5. Finite State Machine Control: ALUSrcA=0 IorD=0,IRwrt ALUSrcB=01 ALUOp=000 PCwrite=1 PCSource=00 ALUSrcA=0 ALUSrcB=10 ALUop=000 PCwrite PCSource =10 ALUSrcA=1 ALUSrcB=00 ALUop=011 PCwritecond PCSource=01 ALUSrcA=1 ALUSrcB=00 ALUop= opcode(2-0) A LUSrcA=1 ALUSrcB=0 0 AlUop=000 IorD= 1 Memwrite IorD=1 RegDst=1 Regwrite Memtore g=0 RegDst= 0 Regwrite Memto Reg=1 Start 0 Instruction Fetch 1 Instruction Decode (op=‘lw’)or(op=‘sw’) op = R-type Op=beq Op=‘jmp’ 2 3 4 5 6 7 8 9 Mem Addr Comp Exec Branch Comp Jmp Comp MemAccs Mem Read Comp R-type Comp

6. Defining The Control Signals: Signal Name\state 0 1 2 3 4 5 6 7 8 9 RegDst 0 0 0 0 0 0 0 1 0 0 RegWrite 0 0 0 0 1 0 0 1 0 0 ALUSrcA 0 0 1 1 1 1 1 1 1 0 MemWrite 0 0 0 0 0 1 0 0 0 0 MemtoReg 0 0 0 0 1 0 0 0 0 0 IorD 0 0 0 1 0 1 0 0 0 0 IRWrite 1 0 0 0 0 0 0 0 0 0 PCWrite 1 0 0 0 0 0 0 0 0 1 PCWriteCond 0 0 0 0 0 0 0 0 1 0 ALUop000 001 010 011 100 000010000 ALUSrcB 01 10 00 PCSource 00 01 10

7. Test Program: High Level Language Assembly LanguageMachine Language Traditional loop in c: While (save[i] < k) i += 1; Assuming: i -> $s0 k -> $s1 base address of save->$s3 loop: add $t1,$s0,$0 add $t1,$t1,$s3 lw $t0,0($t1) beq $t0,$s1,Exit addi $s0,$s0,1 j loop Exit: add $s2,$0,$0 Exit: 0000 101 1 100 0 000011101000 0110100001110000 101111001000Exit 1000100100011001 1101 loop address 10000000 1100

8. Future modifications: Future modifications: - Make changes in the core instruction set and add instructions like (a) Jump register (b) Shift left logic -Implement the control unit as a Micro Computer using: (a) Micro Instructions (b) Microprogramming. -Make effective use of the registers defined. Conclusion: The above designed CPU can execute a sequence of instructions which include R-type, Data transfer, branching etc., while its operations for programs which include functions is to be tested.

9. Questions Questions

10. Thank you! Thank you!