SystemVerilog. History Enhancement of Verilog Enhancement of Verilog 2002 – accellera publishes SystemVerilog 3.0 2002 – accellera publishes SystemVerilog.

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Presentation transcript:

SystemVerilog

History Enhancement of Verilog Enhancement of Verilog 2002 – accellera publishes SystemVerilog – accellera publishes SystemVerilog accellera publishes SystemVerilog 3.1a accellera publishes SystemVerilog 3.1a 2005 – IEEE standardizes SystemVerilog 2005 – IEEE standardizes SystemVerilog

What’s in it Verilog Verilog Modeling: Modeling: New constructs New constructs Synthesizable Synthesizable Verification: Verification: Testbench automation Testbench automation Assertions Assertions

SV for Modeling Verilog Verilog Interfaces Interfaces Data types: 2 and 4 levels, int, shortint, longint, byte, logic, typedef Data types: 2 and 4 levels, int, shortint, longint, byte, logic, typedef 2-state modeling 2-state modeling Flow control mechanisms: Break, continue, return,… Flow control mechanisms: Break, continue, return,… Casting Casting And much more... And much more...

SV for Verification Generation: Constrained random generation Generation: Constrained random generation Check: Assertions Check: Assertions Coverage Coverage Semaphores Semaphores Test program blocks Test program blocks Classes Classes Inheritance Inheritance And much more … And much more …

Constrained Random Generation Within class Within class Fields should be declared as random Fields should be declared as random class packet; randc bit[7:0] addr; randc bit[7:0] addr; rand bit[7:0] data; rand bit[7:0] data; constraint legal_pkt { constraint legal_pkt { addr == 2; addr == 2; }endclass

Interface Separate communication from functionality Separate communication from functionality A bundle of wires that simplifies hierarchical connections A bundle of wires that simplifies hierarchical connections The block ‘uses’ an interface The block ‘uses’ an interface

Available Tools Training Training Consulting Consulting Simulators Simulators SVA packages SVA packages Methodology Methodology Synopsis, Mentor, Cadence Synopsis, Mentor, Cadence Everybody has something Everybody has something

So? Good new capabilities Good new capabilities Modeling and verification in same language Modeling and verification in same language Apparently – all verification services Apparently – all verification services Suitable for designers? Suitable for designers? Synthesizable Complicated to learn Immature tools Immature tools Immature methodology Immature methodology No experience No experience