Detailed Routing: New Challenges

Slides:

Advertisements

Similar presentations

-1- VLSI CAD Laboratory, UC San Diego Post-Routing BEOL Layout Optimization for Improved Time- Dependent Dielectric Breakdown (TDDB) Reliability Tuck-Boon.

Advertisements

EE141 © Digital Integrated Circuits 2nd Wires 1 The Wires Dr. Shiyan Hu Office: EERC 731 Adapted and modified from Digital Integrated Circuits: A Design.

BASIC BLOCKS : PASSIVE COMPONENTS 1. PASSIVE COMPONENTS: Capacitors  Junction Capacitors  Inversion Capacitors  Parallel Plate Capacitors Resistors.

Cadence Design Systems, Inc. Why Interconnect Prediction Doesn’t Work.

UCLA Modeling and Optimization for VLSI Layout Professor Lei He

Analog VLSI Design Nguyen Cao Qui.

Layer 0 Grounding Requirement in terms of noise performance Grounding/Shielding studies with L0 prototype Summary Kazu Hanagaki / Fermilab.

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Chapter 6 – Detailed Routing

04/11/02EECS 3121 Lecture 26: Interconnect Modeling, continued EECS 312 Reading: 8.2.2, (text) HW 8 is due now!

S. Reda EN160 SP’07 Design and Implementation of VLSI Systems (EN0160) Lecture 15: Interconnects & Wire Engineering Prof. Sherief Reda Division of Engineering,

Chapter 6 – Detailed Routing

04/09/02EECS 3121 Lecture 25: Interconnect Modeling EECS 312 Reading: 8.3 (text), 4.3.2, (2 nd edition)

Lecture #25a OUTLINE Interconnect modeling

11/3/2004EE 42 fall 2004 lecture 271 Lecture #27 MOS LAST TIME: NMOS Electrical Model – Describing the I-V Characteristics – Evaluating the effective resistance.

Cmpe222_04des_rules_ppt.ppt1 VLSI Digital Systems Design Process Enhancements and Design Rules.

Interconnessioni e parassiti1 Progettazione di circuiti e sistemi VLSI Anno Accademico Lezione Interconnessioni e parassiti.

Ryan Kastner ASIC/SOC, September Coupling Aware Routing Ryan Kastner, Elaheh Bozorgzadeh and Majid Sarrafzadeh Department of Electrical and Computer.

ELEN 468 Lecture 271 ELEN 468 Advanced Logic Design Lecture 27 Interconnect Timing Optimization II.

Digital Integrated Circuits A Design Perspective

SLIP 2000April 9, Wiring Layer Assignments with Consistent Stage Delays Andrew B. Kahng (UCLA) Dirk Stroobandt (Ghent University) Supported.

7/13/ EE4271 VLSI Design VLSI Routing. 2 7/13/2015 Routing Problem Routing to reduce the area.

A Methodology for Interconnect Dimension Determination By: Jeff Cobb Rajesh Garg Sunil P Khatri Department of Electrical and Computer Engineering, Texas.

Module-3 (MOS designs,Stick Diagrams,Designrules)

Modern VLSI Design 4e: Chapter 7 Copyright  2008 Wayne Wolf Topics Global interconnect. Power/ground routing. Clock routing. Floorplanning tips. Off-chip.

Global Routing.

Pattern Selection based co-design of Floorplan and Power/Ground Network with Wiring Resource Optimization L. Li, Y. Ma, N. Xu, Y. Wang and X. Hong WuHan.

1 Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment Di Wu, Jiang Hu and Rabi Mahapatra Texas A&M University.

CAD for Physical Design of VLSI Circuits

Open Discussion of Design Flow Today’s task: Design an ASIC that will drive a TV cell phone Exercise objective: Importance of codesign.

TSV-Aware Analytical Placement for 3D IC Designs Meng-Kai Hsu, Yao-Wen Chang, and Valerity Balabanov GIEE and EE department of NTU DAC 2011.

ASIC Design Flow – An Overview Ing. Pullini Antonio

Modern VLSI Design 3e: Chapters 1-3 week12-1 Lecture 30 Scale and Yield Mar. 24, 2003.

Thermal-aware Steiner Routing for 3D Stacked ICs M. Pathak and S.K. Lim Georgia Institute of Technology ICCAD 07.

Modern VLSI Design 3e: Chapter 2 Copyright  1998, 2002 Prentice Hall PTR Topics n Design rules and fabrication. n SCMOS scalable design rules. n Stick.

Topics SCMOS scalable design rules. Reliability. Stick diagrams. 1.

Kwangsoo Han‡, Andrew B. Kahng‡† and Hyein Lee‡

EE415 VLSI Design 1 The Wire [Adapted from Rabaey’s Digital Integrated Circuits, ©2002, J. Rabaey et al.]

VLSI Physical Design: From Graph Partitioning to Timing Closure Chapter 6: Detailed Routing © KLMH Lienig 1 What Makes a Design Difficult to Route Charles.

CMOS Fabrication nMOS pMOS.

M ask D esign T raining M ask D esign T raining Page 1 Quality Layout.

VLSI Design Lecture 3: Parasitics of CMOS Wires Mohammad Arjomand CE Department Sharif Univ. of Tech. Adapted with modifications from Harris’s lecture.

Simultaneous Analog Placement and Routing with Current Flow and Current Density Considerations H.C. Ou, H.C.C. Chien and Y.W. Chang Electronics Engineering,

Modern VLSI Design 3e: Chapter 7 Copyright  1998, 2002 Prentice Hall PTR Topics n Power/ground routing. n Clock routing. n Floorplanning tips. n Off-chip.

Update on the Design Implementation Methodology for the 130nm process Microelecronics User Group meeting TWEPP 2010 – Aachen Sandro Bonacini CERN PH/ESE.

VLSI INTERCONNECTS IN VLSI DESIGN - PROF. RAKESH K. JHA

Chapter 4: Secs ; Chapter 5: pp

System in Package and Chip-Package-Board Co-Design

1ISPD'03 Process Variation Aware Clock Tree Routing Bing Lu Cadence Jiang Hu Texas A&M Univ Gary Ellis IBM Corp Haihua Su IBM Corp.

EE 587 SoC Design & Test Partha Pande School of EECS Washington State University

Institute of Applied Microelectronics and Computer Engineering College of Computer Science and Electrical Engineering, University of Rostock VIA DOUBLING.

EE141 © Digital Integrated Circuits 2nd Manufacturing 1 Manufacturing Process -II Dr. Shiyan Hu Office: EERC 518 Adapted and modified from Digital Integrated.

UNIT II CIRCUIT DESIGN PROCESSES

EE4271 VLSI Design VLSI Channel Routing.

Wires & wire delay Lecture 9 Tuesday September 27, 2016.

The Interconnect Delay Bottleneck.

Manufacturing Process -II

Layout of CMOS Circuits

Geometric Design Rules

Crosstalk If both a wire and its neighbor are switching at the same time, the direction of the switching affects the amount of charge to be delivered and.

Chapter 4 Interconnect.

Duckhwan Kim and Saibal Mukhopadhyay

3. Advanced Rules & Models

Electrical Rules Check

VLSI Design CMOS Layout

Puneet Gupta1 , Andrew B. Kahng1 , Youngmin Kim2, Dennis Sylvester2

Reducing Clock Skew Variability via Cross Links

EE4271 VLSI Design, Fall 2016 VLSI Channel Routing.

Presentation transcript:

Detailed Routing: New Challenges

Detailed Routing: New challenges Manufacturers use different wire widths Vias connecting wires of different widths  block additional routing resources on the layer with the smaller wire pitch

Detailed Routing: New challenges Representative layer stacks for 130 nm - 32 nm technology nodes U2 W1 U1 E2 E2 E1 E1 B3 E1 B3 B2 B2 B2 B3 B1 M6 B1 B2 C2 B1 M5 M5 B1 C1 M5 M4 M4 M4 M4 M4 M3 M3 M3 M3 M3 © 2011 Springer Verlag M2 M2 M2 M2 M2 M1 M1 M1 M1 M1 130 nm 90 nm 65 nm 45 nm 32 nm

Detailed Routing: New challenges Manufacturing yield: a key concern in detailed routing Redundant vias and wiring segments as backups (via doubling and non-tree routing) Manufacturability constraints (design rules) become more restrictive  complicate detailed routing Example: design rules specify minimum allowed spacing between wires and vias depending on their widths and proximity to wire corners. Example: Recent spacing rules take into account multiple neighboring polygons.

Via Doubling

Detailed Routing: New challenges Detailed routers must account for manufacturing rules and the impact of manufacturing faults Via defects/performance degradation (from misalignments): Via doubling during or after detailed routing Area penalty Interconnect defects: Non-tree routing: Add redundant wires to already routed nets (postprocess) Antenna-induced defects:

Antenna Effect Recent DFM Issue Long metal lines and vias introduce antenna violations. Conductor layers fabricated from lowest layer to highest layer. The etch process builds up the electrical charges on metal layers. These charges cause a high voltage spike, which may destroy the gates connected to the metals.

Antenna Effect A long line connected to gate only can cause failure Not a problem after chip is complete since every net has at least one driver Driver (diffusion) Load (poly) M1 M2 But, we can have a problem during manufacturing Here is the same net after M1 is built, but not yet M2 Driver (diffusion) Load (poly) M1

Antenna Effect Antenna violation Diffusion Sink 1 Sink 2 ©[Wu]

Antenna Effect Antenna Violations: Metal area antenna rule: the maximum limit to the ratio of the metal line area to the connected gates area. R1 = Am / (W.L)

Antenna Rules Violations to the above antenna rules in every metal layer have to be fixed before the chip tapeout. Each metal layer may have various upper limit rules based on the process specifications. 0.18 (0.13) um technology: the maximum length of an “antenna” wire ≈ 500 um (20 um). Process-Induced Damage Rules (otherwise known as “Antenna Rules”)- General Requirements. http://www.mosis.org/Technical/Designrules/guidelines.html#antenna

Antenna Avoidance Jumper Insertion: Router inserts jumpers for long metals from low-level metals to upper-level layers. The jump cuts the long metals in the low-level layers to disconnected pieces. based on the fact that wire segments on top routing layers are normally fabricated at the end Antenna violation Diffusion Gate Jumper insertion Diffusion Gate

Antenna Avoidance Jumper Insertion: Disadvantage: jumpers introduce extra vias  Degrade both manufacturing yield and circuit timing performance Jia Wang, Hai Zhou, “Optimal Jumper Insertion for Antenna Avoidance under Ratio Upper-Bound,” DAC 2006.

Antenna Avoidance Diode Insertion: Disadvantages: Place and route design adds the PN junction diodes to the unused area of the chip. Connected to the wire segment. Leaks the current to the ground when a high voltage spike occurs. Disadvantages: Depends on placement space Diodes present extra capacitive load to the signal nets they are attached to.

Antenna Avoidance Layer Assignment: Reduce antenna length by layer assignment. Antenna violation Diffusion Gate Jumper insertion Diffusion Gate Layer assignment Diffusion Gate Di Wu, Jiang Hu and Rabi Mahapatra, “Coupling Aware Timing Optimization and Antenna Avoidance in Layer Assignment,” ISPD 2005.