1 EE 501 Fall 2009 Design Project 1 Fully differential multi-stage CMOS Op Amp with Common Mode Feedback and Compensation for high GB

Major components Input differential pair Cascoding for boosting DM gain, CMRR Second gain stage Compensation Common mode feedback Biasing circuits VDD independent current reference (T independence not required for this project but is for next project) Start up circuit 2

Input differential pair NMOS input vs PMOS input –Transconductance gain gm requirement –Noise consideration Area, mismatch, and offset voltage issues Common mode rejection –Tail current source: cascode or not –Effects on CMRR, ICMR Input common mode range –Choice of telecopic vs folded cascode –Choice of VEB’s and Vbias for cascode 3

4 What are the advantages/disadvantages of cascoding M5? Which one offers better differential signal virtual ground at S1/S2? Which one offers better Vicm-min? Which one offers better Vicm rejection? Which one offers better power supply rejection? Which one is more area efficient?

5 What are the advantages/disadvantages of NMOS input vs PMOS input? Which one offers better differential signal transconductance? Which one offers better 1 st stage – 2 nd stage current split considerations? Which one offers better 1/f noise contribution? Which one offers better input referred thermal noise? Which one offers better off set voltage?

Cascoding Telescopic cascode Folded cascode 6

7 Telescopic N-input

8 Telescopic P-input

9 Folded cascode P-input

Second gain stage NMOS input PMOS input Current source load –Cascode load 10

Compensation Miller compensation Rz-Cc compensation –Implementation –Process tracking bias Cc feeding back to cascode Cc feeding back to triode node 11

Common mode feedback 12

Biasing circuit 13

VDD independent reference 14

Startup circuit 15

16

17 First stage bias constraints: Vbb = Vdd – |Vtp| – Veb3 Vxx < Vdd – Vsdsat3 – |Vtp| – Veb3c Vyy < Vdd – Vsdsat3 – Vsdsat3c + Vtn1c Vicm > Vicmmin = Vss + Vdssat7 + Vtn1 + Veb1 Vicm < Vicmmax = Vyy – Vdssat1c Vicmr = Vicmmax – Vicmmin <Vdd – Vss – Vsdsat3 – Vsdsat3c – Vdssat7 – Vdssat1c + Vtn1c – Vtn1 – Veb1 This must > specification

18 Second stage bias constraints: Vo+ < Vdd – Vsdsat6 Vo+ > Vss + Vdssat7 Vzz does not have to be the same as that in first stage Vo1- is not fixed, Vsdsat5 is varying with signal. Vo1 needs to be able to swing high enough to turn off M6, so Vo1max >= Vdd – |Vtp| Vo1 needs to be able to swing low enough for M6 to provide 2*I7=2*I6Q for charging CL, so Vo1min <= Vdd – |Vtp| – sqrt(2)Veb6Q Vo1DSW = Vo1max – Vo1min >= sqrt(2)Veb6Q This Vo1 swing range should be subtracted from the max V_ICMR

19 Inter-stage bias constraints: Vo1 range must accommodate Vg6 needs, and Vg6 ranges from Vdd – |Vtp| to Vdd – Vtp| – sqrt(2)*Veb6Q So worst case Vsdsat6: sqrt(2)*Vsdsat6Q Vo+ should be clear of this. If Vo range is symmetric, this gives enough room to put a cascode on M7 to reduce ro and Co. Therefore we need: Vsdsat3+Vsdsat3c < |Vtp| so that when Vg6 = Vdd–|Vtp| M3 and M3c are still in saturation. We also need: Vyy < Vdd – |Vtp| – sqrt(2)*Veb6Q + Vtn1c so that when Vg6 is the lowest M1c is still in saturation. Vicmmax = Vyy – Vdssat1c < Vdd – |Vtp| – sqrt(2)*Veb6Q – Vdssat1c + Vtn1c Vicmr <Vdd – Vss – |Vtp| – sqrt(2)*Veb6Q – Vdssat7 – Vdssat1c + Vtn1c – Vtn1 – Veb1

20 Slew rate constraints To charge and discharge CL and Cc, current goes from Vo node into or out of these caps. Cc dVo/dt + CL dVo/dt = I6–I7 max|dVo/dt| <= I7/(CL+Cc) The other end of Cc goes to Vo1 node. Cc dVo/dt + I3 = I1 max |dVo/dt| <= I1Q / Cc If SR is limiting factor, we don’t want to waste any current, and we should have SR = I6Q/(CL+Cc) = I1Q / Cc I6Q : I1Q = (CL+Cc) : Cc This significantly limits freedom in Cc and current split choices.

21 If SR is not the performance limiter, can have the Cc charge discharge slower than CL. In this case: SR = I1/Cc If we have put most of the current into 2 nd stage, and chosen Cc to be large compared to CL (CL/Cc ratio small), SR can be small. This leads to constant slope slewing in large size step response and in large magnitude sinusoidal output at near GB frequencies. This in turn leads to increased nonlinearity at high frequencies and high signal magnitudes.

22

23 Design steps for max GB 1.From total power allowance, compute I tot I tot = P tot /(VDD-VSS) 2.Assume that about 5 to 10 % of the current budget will go to reference and biasing circuits, 90 to 95% is available for 1 st and 2 nd stages. As a starting point, take I6 = ¾ I tot 3.Sizing of M6 –For high speed, take small L6, e.g. L6 = L_min or 1.5L_min –For maximum GB, we maximize |p2| W6 = CL/(2C_j L_drain + C_ox L6) –Compute: Cdb6 = Cj L_drain W6 + 2C_jsw(L_drain+W6) Cgs6 = C_ox W6 L6 gm6 = sqrt(2 I6 uC_ox W6/L6) |p2| = gm6 / (CL + Cgs6 + 2Cdb6) ≈ gm6 / 2CL

24 Design steps for max GB 4.Select Cc: Cc <= min{0.5 CL, 0.4 I_tot / SR} e.g. take Cc = 0.2 CL 5.Compute gm1 and I5 I5/2 >= SR * Cc, and watch I5 + I6 to be about 0.9 I_tot if I5 too large, reduce Cc Let GB = |p2|,  gm1/Cc = gm6/2CL  gm1 = gm6 * Cc/2CL,  0.1gm6 6.Size M1/M2: Take L1 to be 1.5 or 2 L_min W1 = gm1^2 L1 /{uC_ox I7} If 1/f is concern, increase L1 and W1 together. 7.In the cascoded case, Vds3 and Vds4 are matched. Size (W/L)3 so that Veb3 to be about 1/3 |VTP|

25 Design steps for max GB 8.M7, M5 and M0 all share the same Vgs that comes from the biasing circuit Select a suitable VEB of about 0.3 V for them Select the same L for all three W5 = 2 I5 / VEB^2 / uC_ox W7 = 2 I7 / VEB^2 / uC_ox Take W0 to be about 5% W6 so that its current is about 5% 9.Sizing M8, M9, Rz Let M8 have the same L as M5 W8 to W5 ratio to be the same as W0 to W6 ratio Let M9 have the same W/L as M8, Rz have the same L Perform parametric scan of W for Rz, to achieve best PM

26  2c  V in- CLCL   4c  1c  V in+   3c V yy  V DD  C vovo V DD 

27 Design steps for max GB 10.You can size M3c and M4c to be about the same as M3 and M4 Vdssat3c,4c are also about Veb3 Vdd-Vd3c is about 3 or 4 time Veb3 This makes it easy to ensure both M3 and M3c to be in saturation 11.Size the resistor and watch how Vd3 changes Choose the resistor value so that Vd3 is right in the middle of Vdd and Vd3c This gives Vds3 = Vds3c = ½ Vgs3 = ½ (1 + 1/3)VTP = 2/3 VTP Both M3 and M3c are in saturation Since Vds4 = Vds3, M4 is in saturation Vds4c = Vgs5 – Vds4 = Vtp+Veb5 -2/3Vtp =1/3Vtp +Veb5 As long as Veb5 > 0, M4c is in saturation

28  2c V in- CLCL   4c  1c V in+   3c  V DD  C vovo V DD   3B 4B 5B

29 Design steps for max GB 12.Size M1c and M2c to be about the same as M1,2 13.Size M1B and M2B to have W/L ratio that is about 5 to 10% of M1 Total current in M1B M2B is about 5 to 10% of I7 Vdd-Vd3c is about 3 or 4 time Veb3 This makes it easy to ensure both M3 and M3c to be in saturation 14.Match M3B and M4B Their sizes are non-critical But use reasonable Veb 15.Size M5B to create the correct bias for M1c,2c Choose its W/L ratio so that Veb5b is 3 to 4 times Veb1 This guarantees saturation of M1,2 and M1c,2c

30 Bias generator

31 Design steps for max GB 16.For simplicity, you can have all M1 through M4 in the bias circuit to be the same size M6 is the tail current source in first stage M5 is not needed in the self biasing design Let W/L ratio of M1-4 to be about 1/10 of (W/L)_tail This creates a current of about 1/10 I7 M4 and M5 has better match than M6 and M1 You could flip up down for better matching 17.Size resistor Scan resistor value to achieve I1, I2 that you want 18.Size shaded part so that Current in M8 is tiny Vg8 =Vg7 > 3Vtn but < 3Vtn + Veb1 + Veb2

32  c  V in- CLCL   c  1c  V in+   3c V yy  V DD  C vovo V DD  Can feed to here also

33 The Miller capacitor Cc sees an amplifier consisting of a common gate amplifier M4c followed by a common source amplifier M6. This amplifier’s low frequency gain is The miller capacitance seen at D4 is very large: The impedance at this node is: 1/g m4c This node gives the lowest frequency pole which determines the bandwidth of the amplifier:

34 The DC gain of the amplifier is The gain bandwidth product is then The max rate of V cc can change is when all of first stage current goes to charge C C. Hence, slew rate is

35  c  V in- CLCL   c V DD  C vovo V DD  To calculate zero: Set Vo = 0 and all DC voltage to gnd V d4 = Vcc V g6 = Vcc*g m4c /g 01 Icc + g m6 V g6 =0 sCc + g m6 g m4c /g 01 =0 Z1= – g m6 g m4c /(g 01 Cc) At extremely high frequency! Cannot be used to cancel a pole near unity gain frequency!

36  c  V in- CLCL   c V DD  C vovo V DD  Alternative compensation for removing right-half plane zero: Noncascode version:

37

38

39

40

41

42 1.Need to add start-up circuit 2.Add MOSCAPs between VBP and VDD, and between VBN and VSS 3.NMOS W ratio and R determines current value 4.Cascode to improve supply sensitivity 5.Or use a regulate amp 6.VBN and VBP may be directly used as biasing voltage for non-critical use

43

44