Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt 1 FACULTY OF ENGINEERING AND ARCHITECTURE.

Slides:

Advertisements

Similar presentations

ECE 667 Synthesis & Verificatioin - FPGA Mapping 1 ECE 667 Synthesis and Verification of Digital Systems Technology Mapping for FPGAs D.Chen, J.Cong, DAOMap.

Advertisements

EELE 367 – Logic Design Module 2 – Modern Digital Design Flow Agenda 1.History of Digital Design Approach 2.HDLs 3.Design Abstraction 4.Modern Design Steps.

Lecture 9: Coarse Grained FPGA Architecture October 6, 2004 ECE 697F Reconfigurable Computing Lecture 9 Coarse Grained FPGA Architecture.

Graduate Computer Architecture I Lecture 16: FPGA Design.

Hardwired networks on chip for FPGAs and their applications

1 VLSI DESIGN USING VHDL Part II A workshop by Dr. Junaid Ahmed Zubairi.

Generic Multiplexers: Parameters Discussion D2.5 Example 8.

1 DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen, Jacon Cong ICCAD 2004 Presented by: Wei Chen.

02/02/20091 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

Dr. Turki F. Al-Somani VHDL synthesis and simulation – Part 3 Microcomputer Systems Design (Embedded Systems)

Yu Hu1, Satyaki Das2 Steve Trimberger2, and Lei He1

1/31/20081 Logic devices can be classified into two broad categories Fixed Programmable Programmable Logic Device Introduction Lecture Notes – Lab 2.

Decoders and Encoders Sections 3-5, 3-6 Mano & Kime.

Logic Verification 1 Outline –Logic Verification Problem –Verification Approaches –Recursive Learning Approach Goal –Understand verification problem –Understand.

ECE 331 – Digital System Design

EE 367 – Logic Design Lecture #17

CSET 4650 Field Programmable Logic Devices Dan Solarek VHDL Behavioral & Structural.

StaticRoute: A novel router for the dynamic partial reconfiguration of FPGAs Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt 2/9/2013.

RUN-TIME RECONFIGURATION FOR AUTOMATIC HARDWARE/SOFTWARE PARTITIONING Tom Davidson, Karel Bruneel, Dirk Stroobandt Ghent University, Belgium Presenting:

Juanjo Noguera Xilinx Research Labs Dublin, Ireland Ahmed Al-Wattar Irwin O. Irwin O. Kennedy Alcatel-Lucent Dublin, Ireland.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

Automating Shift-Register-LUT Based Run-Time Reconfiguration Karel Heyse, Brahim Al Farisi, Karel Bruneel, Dirk Stroobandt

Overview Dynamic reconfiguration of FPGAs:

Gene Matching Using JBits Steven A. Guccione Eric Keller.

An automatic tool flow for the combined implementation of multi-mode circuits Brahim Al Farisi, Karel Bruneel, João Cardoso, Dirk Stroobandt.

Designing with FPGAs ELEC 418 Advanced Digital Systems Dr. Ron Hayne Images Courtesy of Thomson Engineering.

POWER-DRIVEN MAPPING K-LUT-BASED FPGA CIRCUITS I. Bucur, N. Cupcea, C. Stefanescu, A. Surpateanu Computer Science and Engineering Department, University.

LOPASS: A Low Power Architectural Synthesis for FPGAs with Interconnect Estimation and Optimization Harikrishnan K.C. University of Massachusetts Amherst.

System Arch 2008 (Fire Tom Wada) /10/9 Field Programmable Gate Array.

Automated Design of Custom Architecture Tulika Mitra

CPLD (Complex Programmable Logic Device)

J. Christiansen, CERN - EP/MIC

CprE / ComS 583 Reconfigurable Computing

Array Synthesis in SystemC Hardware Compilation Authors: J. Ditmar and S. McKeever Oxford University Computing Laboratory, UK Conference: Field Programmable.

CHAPTER 9 MULTIPLEXERS, DECODERS, AND PROGRAMMABLE LOGIC DEVICES

A Routing Approach to Reduce Glitches in Low Power FPGAs Quang Dinh, Deming Chen, Martin D. F. Wong Department of Electrical and Computer Engineering University.

ENG241 Digital Design Week #8 Registers and Counters.

Han Liu Supervisor: Seok-Bum Ko Electrical & Computer Engineering Department 2010-Feb-2.

DAOmap: A Depth-optimal Area Optimization Mapping Algorithm for FPGA Designs Deming Chen and Jason Cong Computer Science Department University of California,

CprE / ComS 583 Reconfigurable Computing Prof. Joseph Zambreno Department of Electrical and Computer Engineering Iowa State University Lecture #4 – FPGA.

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

1 A Min-Cost Flow Based Detailed Router for FPGAs Seokjin Lee *, Yongseok Cheon *, D. F. Wong + * The University of Texas at Austin + University of Illinois.

ECE 331 – Digital System Design Multiplexers and Demultiplexers (Lecture #13)

Timing-Driven Routing for FPGAs Based on Lagrangian Relaxation

Evaluating and Improving an OpenMP-based Circuit Design Tool Tim Beatty, Dr. Ken Kent, Dr. Eric Aubanel Faculty of Computer Science University of New Brunswick.

Introduction to FPGA Tools

CS/EE 3700 : Fundamentals of Digital System Design

In-Place Decomposition for Robustness in FPGA Ju-Yueh Lee, Zhe Feng, and Lei He Electrical Engineering Dept., UCLA Presented by Ju-Yueh Lee Address comments.

Logic and Computer Design Fundamentals, Fifth Edition Mano | Kime | Martin Copyright ©2016, 2008, 2004 by Pearson Education, Inc. All rights reserved.

Routing Wire Optimization through Generic Synthesis on FPGA Carry Hadi P. Afshar Joint work with: Grace Zgheib, Philip Brisk and Paolo Ienne.

Lecture 17: Dynamic Reconfiguration I November 10, 2004 ECE 697F Reconfigurable Computing Lecture 17 Dynamic Reconfiguration I Acknowledgement: Andre DeHon.

Lecture #17 Page 1 ECE 4110–5110 Digital System Design Lecture #17 Agenda 1.MSI Multiplexers 2.MSI Encoders Announcements Test 1 closed book, Wednesday.

QUIZ What Circuit is this ?. Entity (The Object) -- Entity informs about the circuit’s interface -- signals entity my_circuit is port (L0, L1, L2, L3.

1 Introduction to Engineering Spring 2007 Lecture 18: Digital Tools 2.

Fundamentals of Digital Signal Processing יהודה אפק, נתן אינטרטור אוניברסיטת תל אביב.

1 Architecture of Datapath- oriented Coarse-grain Logic and Routing for FPGAs Andy Ye, Jonathan Rose, David Lewis Department of Electrical and Computer.

1 Introduction to Engineering Spring 2007 Lecture 19: Digital Tools 3.

Runtime-Quality Tradeoff in Partitioning Based Multithreaded Packing

Registers and Counters

ENG2410 Digital Design “Combinational Logic Design”

ECE 4110–5110 Digital System Design

Introduction Introduction to VHDL Entities Signals Data & Scalar Types

Reconfigurable Computing

Field Programmable Gate Array

Field Programmable Gate Array

Field Programmable Gate Array

Cryptol aided formal verification of VHDL code

FPGA Logic Synthesis using Quantified Boolean Satisfiability

FIGURE 5-1 MOS Transistor, Symbols, and Switch Models

CprE / ComS 583 Reconfigurable Computing

Presentation transcript:

Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt 1 FACULTY OF ENGINEERING AND ARCHITECTURE Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

FPGA configuration I/O block Logic Block Programmable routing FF 0 A B O LUTLUT 2 Configuration { … } Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Parameterized Configuration SpecializedConfigurations { A+B AB A 1 } { } * K. Bruneel and D. Stroobandt, “Automatic Generation of Run-time Parameterizable Configurations,” FPL { } { } { } AB Parameters Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Applications Dynamic Circuit Specialization – Circuit optimization (smaller, faster, …) using runtime reconfiguration Circuit Specialization – Hard coded settings of devices Very fast generation of specialized configurations 4Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Static Connections What’s new in this work A+B A 1 FF 0 A B O LUTLUT Tunable LUTs (TLUT) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Tunable Connections (TCON) AB1 What’s new in this work 6 0 A+B A 1 FF 0 A B O LUTLUT Tunable LUTs (TLUT) Mapping functionality to Tunable Connections (and TLUTs) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Outline FPGA configuration Applications What’s new in this work Toolflow Technology mapping Experiments Conclusion and Future work 7Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 88 Parameterized HDL design Parameterized configuration Specialized configuration Parameter values Synthesis Technology mapping PlacementRouting Evaluate Boolean fn. Generic Stage Specialization Stage Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 99 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting a0a0 I1I1 I2I2 p O a1a1 a2a2 a3a3 I0I0 a4a4 entity multiplexer is port( --BEGIN PARAM sel : in std_logic_vector(1 downto 0); --END PARAM in : in std_logic_vector(3 downto 0); out : out std_logic ); end multiplexer; architecture behavior of multiplexer is begin out <= in(conv_integer(sel)); end behavior; Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 10 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting Tunable LUT network I1I1 I2I2 O I0I0 a0a0 I1I1 I2I2 p O a1a1 a2a2 a3a3 I0I0 a4a4 TLUT Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 11 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting TLUT & TCON network I1I1 I2I2 O I0I0 I3I3 C(P)C(P) Tunable Connection (TCON) TCON TLUT TCON Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 12 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting p 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬p

Toolflow 13 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting 1 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬1

Toolflow 14 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting 0 2 Tunable Connections Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012 ¬0

Technology mapping 15 a0a0 I1I1 I2I2 I3I3 O a1a1 a2a2 a3a3 I0I0 a4a4 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Algorithm Minimal depth mapping 1.Cone enumeration: Finding all feasible cones per node 2.Cone ranking: Selecting best feasible cone per nod e 3.Cone selection: Selecting cones that provide covering 16Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Feasibility: LUT Cone with 3 input nodes = LUT-feasible (3 input LUT) 17 a0a0 I1I1 I2I2 a1a1 a3a3 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Feasibility: TLUT Cone with 3 input nodes that aren’t parameters = TLUT-feasible (3 input LUT) 18 a0a0 I1I1 I2I2 a1a1 a3a3 a2a2 p Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Feasibility: TCON Equivalent to multiplexer controlled by function of parameters = TCON-feasible 19 I1I1 I2I2 p a0a0 a2a2 I2I2 I1I1 p a1a1 Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

TLC supergate One TLUT with TCONs attached to its inputs 20 TLC TCON TLUT TCON … Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Feasibility: TLC supergate Equivalent to multiplexer controlled by function of parameters and LUTs at its inputs = TLC-feasible 21 p I1I1 I2I2 I3I3 I4I4 q a0a0 a2a2 a1a1 I1I1 I2I2 b0b0 I3I3 I4I4 c1c1 c0c0 pq 0 LUT

Feasibility calculation 22 Based on cone function: Ψ a0a0 a2a2 a1a1 I1I1 I2I2 b0b0 I3I3 I4I4 c1c1 c0c0 pq Ψ(I 1,I 2,I 3,I 4,p,q)

Feasibility calculation Using Binary Decision Diagram of cone function 23Ghent University – Computer Systems Lab – FPL 2012 – 30 August Ψ

Feasibility calculation Using Binary Decision Diagram of cone 24 Ψ f(p,q) k(I 1,I 2,l 4 )m(I 1,I 2,l 3 ) n(I 1,I 3,l 5 ) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Feasibility calculation Using Binary Decision Diagram of cone 25 Ψ f(p,q) s(I 1 )t(I 2 ) v(I 3 ) Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

EXPERIMENTAL RESULTS 26Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Area and depth 27Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

TLC supergate 28Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Execution time and scaling behaviour 29Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Conclusion Automatically map functionality to reconfigurable routing Creates smaller and faster mapping results Part of new toolflow to quickly create specialized configurations 30Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Mapping Logic to Reconfigurable FPGA Routing Karel Heyse Karel Bruneel and Dirk Stroobandt 31 FACULTY OF ENGINEERING AND ARCHITECTURE Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Acknowledgement Supported by European Commission FP7 project: The author is supported by a Ph.D. grant of the FWO- Vlaanderen 32Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012

Toolflow 33 Parameterized HDL design Parameterized configuration Synthesis Technology mapping PlacementRouting Tuneable LUT TLUT g(P) Tuneable Connection TCON LUT Ghent University – Computer Systems Lab – FPL 2012 – 30 August 2012