1 Lecture #10 EGR 277 – Digital Logic Multiplexers (Data Selectors) A multiplexer (MUX) is a device that allows several low-speed signals to be sent over one high-speed output line. “Select lines” are used to specify which input signal is sent to the output. A demultiplexer (DEMUX) performs the opposite task as the multiplexer: it divides one high-speed input signal into several low-speed components. Multiplexers and demultiplexers must be synchronized so that the proper signals are selected. This type of multiplexing is referred to as time-division multiplexing (TDM). Another type of multiplexing is frequency-division multiplexing (FDM), which is typically covered in a communications course. Multiplexed signals are typically transmitted in precisely organized manners according to a set of rules for transmission called a protocol. An example of multiplexed signals is shown below using two TTL devices. Reading Assignment: Chapters 4 and 7 in Digital Design, 3 rd Edition by Mano Handout: Data sheet for GAL22V10 Programmable Logic Device (PLD)

2 Lecture #10 EGR 277 – Digital Logic Example – Sketch Y for the 4x1 MUX above for A, B, C, D, S1, and S0 shown below.

3 Lecture #10 EGR 277 – Digital Logic Multiplexer Design – Develop a simple Boolean expressions for a multiplexer output. Draw the multiplexer circuit.

4 Lecture #10 EGR 277 – Digital Logic Expanding multiplexers – Show how two 4 x 1 multiplexers and a 2 x 1 multiplexer can be used to create an 8 x 1 multiplexer.

5 Lecture #10 EGR 277 – Digital Logic Demultiplexers and decoders A decoder can also serve as a demultiplexer if the decoder has either: Active-LOW outputs and an active-LOW enable line or Active-HIGH outputs and an active-HIGH enable line Examples: A 4x2 decoder can also serve as a 4x1 DEMUX An 8x3 decoder can also serve as a 8x1 DEMUX A 16x4 decoder can also serve as a 16x1 DEMUX Example: Illustrate how the can be used as a 2x4 decoder or a 1x4 demultiplexer.

6 Lecture #10 EGR 277 – Digital Logic Implementing Boolean functions using multiplexers A multiplexer with N select lines can be used to implement a Boolean function of (N+1) variables. For example, a 4x1 MUX has two select lines, so it can be used to implement a Boolean function with three input variables as shown below. Example: To see how this might work, determine the truth table for F from the multiplexer circuit shown below.

7 Lecture #10 EGR 277 – Digital Logic Example: To see how this might work, determine the truth table for F from the multiplexer circuit shown below. A) First use a truth table to determine the output in each case. B) Shown below is multiplexer implementation table. Circle the minterms. C) Fill in the bottom line of the table as follows: If both minterms circled: 1 If no minterms circled: 0 If only the minterm in the top row circled: A’ If only the minterm in the bottom row circled: A D) Note how the numbers in the bottom row of the table indicate the circuit connections to make.

8 Lecture #10 EGR 277 – Digital Logic Procedure - Implementing Boolean functions with multiplexers: 1) Determine the size multiplexer needed. For a function with N inputs, a MUX with N-1 select lines is needed. 2) Determine the minterms for the function. 3) Draw the MUX implementation table. Note that the minterm ordering depends on how the inputs are connected to the MUX. The simplest way is to connect the LSB of the input to the LSB of the select lines. 4) Circle the minterms in the MUX implementation table. Use this information to determine the connections to the inputs of the MUX as follows: A) If both minterms circled: connect 1 to the input B) If no minterms circled: connect 0 to the input C) If only the minterm in the top row circled: connect A’ (or variable on left of MUX implementation table) D) If only the minterm in the bottom row circled: connect A (or variable on left of MUX implementation table)

9 Lecture #10 EGR 277 – Digital Logic Example: Implement the function f(A, B, C, D) = A’C’ + A’B + BC’D’ + AB’CD’ using an 8 x 1 multiplexer with the input variables connected as shown.

10 Lecture #10 EGR 277 – Digital Logic Example: (same as last example except different input connections) Implement the function f(A, B, C, D) = A’C’ + A’B + BC’D’ + AB’CD’ using an 8 x 1 multiplexer with the input variables connected as shown.

11 Lecture #10 EGR 277 – Digital Logic Programmable Logic Devices (PLD’s) PLD’s are used to build customized circuits. PLD’s contain arrays containing hundreds or thousands of AND, OR, and NOT gates (and flip-flops also – to be covered in the next chapter). PLD’s are programmed to make interconnections between the gates, thus yielding a single IC that might easily replace huge circuits. PLD’s are often erasable so that they can be easily reprogrammed. PLD’s may be: mask programmable – factory programmed. Customized for the user. Only feasible in huge quantities. Field programmable – programmed by the user.

12 Lecture #10 EGR 277 – Digital Logic In order to program a PLD, the following items are required:  PLD – there are numerous manufacturers of PLD’s. They come in various sizes with internal structures that are equivalent to hundreds, thousands, or tens of thousands of equivalent gates.  PLD programming software – this software allows the user to specify exactly how the circuit should perform. Functions might be specified in terms of truth table, Boolean expressions, state equations, and by several other methods. The PLD programming software would compile the information and produce a JEDEC file, which is essentially an industry standard binary file containing information on how to make connections within a given PLD. There are numerous brands of PLD programming software, including PLDShell, MAX PLUS II, PSPICE, ABEL, CUPL, XILINX, ORCAD, and many others.  PLD programmer – this piece of hardware might contain a universal socket that could hold various types of PLD’s. The PLD software produces a JEDEC file which is downloaded into the programmer. The programmer can typically program, copy, erase, and verify the contents of PLD’s.

13 Lecture #10 EGR 277 – Digital Logic There are several types of architectures that are used in PLD’s. Two of the simplest are: 1. Programmable Logic Arrays (PLA’s)  contain AND-OR arrays for implementing SOP expressions  a typical size array might contain 16 inputs, 48 product terms, and 8 sum terms  both complemented and uncomplemented outputs are typically available  Figure 7-14 in the text by Mano shows a small PLA (for illustration) that uses 3 inputs, 3 product terms, and 2 outputs (use X’s to indicate programmed connections). complemented and uncomplemented A' B C D F = A'CD' an X is used to indicate a programmed connection Programming notation A B' C' D' A A' outputs are available

14 Lecture #10 EGR 277 – Digital Logic Example: Use the PLA shown in Figure 7-14 to implement F1(A,B,C) =  (0,1,2,6) and F2(A,B,C) =  (0,1,3,5,7).

15 Lecture #10 EGR 277 – Digital Logic 2. Programmable Array Logic (PAL’s)  contain fixed OR gates with programmable AND’s only  there are no shared product terms except through feedback connections  each OR has a fixed number of product terms, so if more product terms are required, they must be obtained through feedback  a typical size section (or macrocell) might contain 8 AND’s into 1 OR. A typical PAL might contain 8 macrocells.  Figure 7-16 in the text by Mano shows a small PAL (for illustration) that uses 4 macrocells, each containing 3 product terms and a fixed OR gate. The following notation is used to indicate programmed connections in the array:  PAL’s are used in the EGR 278 lab. The PAL used is the GAL22V10’s containing 10 macrocells and 22 input/output connections. Data Sheet - Look at the data sheet for the GAL22V10. The last sheet shows the logic diagram/fuse map. Note the number of product (AND) terms for each of the fixed OR gates.

16 Lecture #10 EGR 277 – Digital Logic Example: Implement F1(A,B,C,D) =  (2,3,5-7,10,12-14) and F2(A,B,C,D) =  (2,3,6-12,14) using the PAL shown in Figure 7-16.