Testing of Digital Systems: An Introduction Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals Dr. Aiman H. El-Maleh Computer Engineering Department King Fahd University of Petroleum & Minerals

1-2 OutlineOutline n Introduction n Manufacturing Cost n Defects, Faults, Fault Models n Automatic Test Pattern Generation n Scan Testing Methodology n Built-In Self Test n Conclusions Most figures used in this presentation are taken from Design-for-Test for Digital IC’s and Embedded Core Systems by Alfred L. Crouch. n Introduction n Manufacturing Cost n Defects, Faults, Fault Models n Automatic Test Pattern Generation n Scan Testing Methodology n Built-In Self Test n Conclusions Most figures used in this presentation are taken from Design-for-Test for Digital IC’s and Embedded Core Systems by Alfred L. Crouch.

1-3 VLSI Realization Process Determine requirements Write specifications Design synthesis and Verification Fabrication Manufacturing test Chips to customer Customer’s need Test development

1-4 DefinitionsDefinitions n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect. n Design synthesis: Given an I/O function, develop a procedure to manufacture a device using known materials and processes. n Verification: Predictive analysis to ensure that the synthesized design, when manufactured, will perform the given I/O function. n Test: A manufacturing step that ensures that the physical device, manufactured from the synthesized design, has no manufacturing defect.

1-5 Verification vs. Test n Verifies correctness of design. n Performed by simulation, hardware emulation, or formal methods. n Performed once prior to manufacturing. n Responsible for quality of design. n Verifies correctness of design. n Performed by simulation, hardware emulation, or formal methods. n Performed once prior to manufacturing. n Responsible for quality of design. n Verifies correctness of manufactured hardware. n Two-part process: 1. Test generation: software process executed once during design 2. Test application: electrical tests applied to hardware n Test application performed on every manufactured device. n Responsible for quality of devices. VerificationTest

1-6 Definition of Testing n A known input stimulus is applied to a unit in a known state, and a known response can be evaluated.

1-7 ExampleExample

1-8 Reasons for Testing n Detection: Determination whether or not the device under test (DUT) has some fault. Measurement of defects and quality level Reliability requirement n Diagnosis: Identification of a specific fault that is present on DUT. n Device characterization: Determination and correction of errors in design and/or test procedure. n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT. n Detection: Determination whether or not the device under test (DUT) has some fault. Measurement of defects and quality level Reliability requirement n Diagnosis: Identification of a specific fault that is present on DUT. n Device characterization: Determination and correction of errors in design and/or test procedure. n Failure mode analysis (FMA): Determination of manufacturing process errors that may have caused defects on the DUT.

1-9 Product Manufacturing Cost

1-10 Product Manufacturing Cost n Reduction of silicon cost increasing volume and yield die size reduction (process shrinks or more efficient layout) n Reduction of packaging cost increasing volume, shifting to lower cost packages if possible (e.g., from ceramic to plastic), reduction in package pin count n Reduction in cost of test reducing vector data size reducing the cost of the tester reducing test time n Reduction of silicon cost increasing volume and yield die size reduction (process shrinks or more efficient layout) n Reduction of packaging cost increasing volume, shifting to lower cost packages if possible (e.g., from ceramic to plastic), reduction in package pin count n Reduction in cost of test reducing vector data size reducing the cost of the tester reducing test time

1-11 Main Difficulties in Testing n Miniaturization Physical access difficult or impossible. n Increasing complexity Large amount of test data. n Number of access ports remains constant Long test application time. n High speed High demand on tester’s driver/sensor mechanism and more complicated failure mechanism. n Testing accounts up to 50% of product development efforts. n The key to successful testing lies in the design process. n Miniaturization Physical access difficult or impossible. n Increasing complexity Large amount of test data. n Number of access ports remains constant Long test application time. n High speed High demand on tester’s driver/sensor mechanism and more complicated failure mechanism. n Testing accounts up to 50% of product development efforts. n The key to successful testing lies in the design process.

1-12 Main Difficulties in Testing

1-13 Costs of Testing n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost n Design for testability (DFT) Chip area overhead and yield reduction Performance overhead n Software processes of test Test generation and fault simulation Test programming and debugging n Manufacturing test Automatic test equipment (ATE) capital cost Test center operational cost

1-14 Cost of Manufacturing Test n GHz, analog instruments,1,024 digital pins: ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second n GHz, analog instruments,1,024 digital pins: ATE purchase price= $1.2M + 1,024 x $3,000 = $4.272M n Running cost (five-year linear depreciation) = Depreciation + Maintenance + Operation = $0.854M + $0.085M + $0.5M = $1.439M/year n Test cost (24 hour ATE operation) = $1.439M/(365 x 24 x 3,600) = 4.5 cents/second

1-15 Automatic Test Equipment Components n Powerful computer n Powerful 32-bit Digital Signal Processor (DSP) for analog testing n Test Program (written in high-level language) running on the computer n Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) n Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad) n Powerful computer n Powerful 32-bit Digital Signal Processor (DSP) for analog testing n Test Program (written in high-level language) running on the computer n Probe Head (actually touches the bare or packaged chip to perform fault detection experiments) n Probe Card or Membrane Probe (contains electronics to measure signals on chip pin or pad)

1-16 ADVANTEST Model T6682 ATE

1-17 LTX FUSION HF ATE

1-18 Manufacturing Test Board n The chip will be accessed by the tester at its pins only n A custom (load) board will be made for this purpose n Each pin has a limited number of bits available (e.g., 2 MB) n Test program (set of vectors and tester control) applied at tester speed (may be less than actual chip speed) n Primary goal of manufacturing test is structural verification n The chip will be accessed by the tester at its pins only n A custom (load) board will be made for this purpose n Each pin has a limited number of bits available (e.g., 2 MB) n Test program (set of vectors and tester control) applied at tester speed (may be less than actual chip speed) n Primary goal of manufacturing test is structural verification

1-19 Design For Testability n To take into account the testing aspects during the design process so that more testable designs will be generated. n Advantages of DFT Reduce test efforts. Eases generation of test vectors Eases diagnosis & debugging Reduce cost for test equipments (ATE). Shorten turnaround time. Increase product quality. n Disadvantages of DFT Adds complexity to design methodology Impacts design area, power, speed and package pins n To take into account the testing aspects during the design process so that more testable designs will be generated. n Advantages of DFT Reduce test efforts. Eases generation of test vectors Eases diagnosis & debugging Reduce cost for test equipments (ATE). Shorten turnaround time. Increase product quality. n Disadvantages of DFT Adds complexity to design methodology Impacts design area, power, speed and package pins

1-20 DefectsDefects n Defects: physical problems that occur in silicon n Common Silicon CMOS defects: Gate-oxide shorts Insufficient doping Process or mask errors Metal trace opens Metal trace bridges Open and plugged vias Short to power (Vdd) or Ground (Vss) n Defects: physical problems that occur in silicon n Common Silicon CMOS defects: Gate-oxide shorts Insufficient doping Process or mask errors Metal trace opens Metal trace bridges Open and plugged vias Short to power (Vdd) or Ground (Vss)

1-21 DefectsDefects

1-22 FaultsFaults n Fault is a model of failure mode of defect that relates defect to circuit behavior. n Example Gate-Oxide short shorts transistor’s source to drain (S2D) Modeled by connecting gate to 0 or 1 Transistor Stuck-on or Stuck-off n Behavior resulting from these models may be a high current, a high impedance state or intermittent behavior. n Fault is a model of failure mode of defect that relates defect to circuit behavior. n Example Gate-Oxide short shorts transistor’s source to drain (S2D) Modeled by connecting gate to 0 or 1 Transistor Stuck-on or Stuck-off n Behavior resulting from these models may be a high current, a high impedance state or intermittent behavior.

1-23 Common Fault Models n Single stuck-at faults n Transistor open and short faults n Bridging faults n Delay faults (transition, path) n Memory faults n PLA faults (stuck-at, cross-point, bridging) n Functional faults (processors) n Analog faults n Single stuck-at faults n Transistor open and short faults n Bridging faults n Delay faults (transition, path) n Memory faults n PLA faults (stuck-at, cross-point, bridging) n Functional faults (processors) n Analog faults

1-24 Single Stuck-at Fault Model n Failures represented as an individual wire shorted to Vdd (stuck-at-1) or Vss (stuck-at-0). n Covers many of physical defects. n Number of faults small. n Independent of technology. n Can be used to model other type of faults. n Failures represented as an individual wire shorted to Vdd (stuck-at-1) or Vss (stuck-at-0). n Covers many of physical defects. n Number of faults small. n Independent of technology. n Can be used to model other type of faults.

1-25 ExampleExample

1-26 Multiple Stuck-at Faults n A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. n The total number of multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. n A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. n Statistically, single fault tests cover a very large number of multiple faults. n A multiple stuck-at fault means that any set of lines is stuck-at some combination of (0,1) values. n The total number of multiple stuck-at faults in a circuit with k single fault sites is 3 k -1. n A single fault test can fail to detect the target fault if another fault is also present, however, such masking of one fault by another is rare. n Statistically, single fault tests cover a very large number of multiple faults.

1-27 Transistor (Switch) Faults n MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. n Detection of a stuck-open fault requires two vectors. n Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ). n MOS transistor is considered an ideal switch and two types of faults are modeled: Stuck-open -- a single transistor is permanently stuck in the open state. Stuck-short -- a single transistor is permanently shorted irrespective of its gate voltage. n Detection of a stuck-open fault requires two vectors. n Detection of a stuck-short fault requires the measurement of quiescent current (IDDQ).

1-28 Stuck-Open Example Two-vector s-op test can be constructed by ordering two s-at tests A B V DD C pMOS FETs nMOS FETs Stuck- open (Z) Good circuit states Faulty circuit states Vector 1: test for A s-a-0 (Initialization vector) Vector 2 (test for A s-a-1)

1-29 Stuck-Short Example A B V DD C pMOS FETs nMOS FETs Stuck- short (X) Good circuit state Faulty circuit state Test vector for A s-a-0 I DDQ path in faulty circuit

1-30 Delay Faults n Some defects do not manifest a logical incorrect behavior but appear as an increase in delay n Example Small metal open on a connection trace Logic value still propagates Propagation of value is slowed down n Some defects do not manifest a logical incorrect behavior but appear as an increase in delay n Example Small metal open on a connection trace Logic value still propagates Propagation of value is slowed down

1-31 ExampleExample

1-32 Fault Coverage n Used as measure of test quality

1-33 Types of Testing

1-34 Automatic Test Pattern Generation n Eases generation of test vectors. n Reduces cost of test More efficient test vectors Reduction in cycle time n Provides a deterministic quality metric. n Eases generation of test vectors. n Reduces cost of test More efficient test vectors Reduction in cycle time n Provides a deterministic quality metric.

1-35 Detectable Fault

1-36 Undetectable Fault

1-37 Fault Equivalence n All faults that produce the same faulty function are equivalent. n If one fault is detected, all equivalent faults are detected. n Fault selection only needs to target one of the equivalent faults. n All faults that produce the same faulty function are equivalent. n If one fault is detected, all equivalent faults are detected. n Fault selection only needs to target one of the equivalent faults.

1-38 Fault Equivalence Example

1-39 Stuck-At Fault ATPG

1-40 Path Sensitization Method Circuit Example n Fault Sensitization n Fault Propagation n Line Justification n Fault Sensitization n Fault Propagation n Line Justification

1-41 Path Sensitization Method Circuit Example n Try path f–h–k–L blocked at j, since there is no way to justify the 1 on i 1 0 D D D D D D=1/0 D=0/1

1-42 Path Sensitization Method Circuit Example n Try simultaneous paths f–h–k–L and g–i–j–k–L blocked at k because D-frontier (chain of D or D) disappears 1 D D D D D 1 1 1

1-43 Path Sensitization Method Circuit Example n Final try: path g–i–j–k–L  test found! 0 D D D 1 D D 1 0 1

1-44 Transition Delay Fault ATPG

1-45 Fault Simulation Example 1. Create multiple copies of the netlist for each fault. 2. Apply same vectors to each copy. 3. Compare each copy to good simulation (expected response). 4. Fault is detected if bad circuit and good circuit differ at a detect point. 1. Create multiple copies of the netlist for each fault. 2. Apply same vectors to each copy. 3. Compare each copy to good simulation (expected response). 4. Fault is detected if bad circuit and good circuit differ at a detect point.

1-46 Test Compaction and Compression

1-47 Sequential Circuits n A sequential circuit has memory in addition to combinational logic. n Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output n Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods n A sequential circuit has memory in addition to combinational logic. n Test for a fault in a sequential circuit is a sequence of vectors, which Initializes the circuit to a known state Activates the fault, and Propagates the fault effect to a primary output n Methods of sequential circuit ATPG Time-frame expansion methods Simulation-based methods

1-48 Example: A Serial Adder FF AnAn BnBn CnCn C n+1 SnSn s-a X X X D D Combinational logic

1-49 Time-Frame Expansion AnAn BnBn FF CnCn C n+1 1 X X SnSn s-a D D Combinational logic S n-1 s-a X D D Combinational logic C n D D X A n-1 B n-1 Time-frame -1 Time-frame 0

1-50 Concept of Time-Frames n If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic n If the test sequence for a single stuck-at fault contains n vectors, Replicate combinational logic block n times Place fault in each block Generate a test for the multiple stuck-at fault using combinational ATPG with 9-valued logic Comb. block Fault Time- frame 0 Time- frame Time- frame -n+1 Unknown or given Init. state Vector 0Vector -1 Vector -n+1 PO 0 PO -1 PO -n+1 State variables Next state

1-51 Example of Sequential Circuit

1-52 Improving Controllability & Observability

1-53 Regular vs. Scan Flip-Flop

1-54 Example Scan Circuit with Scan Chain

1-55 Scan Element Operations n Scan cell provides observability and controllability of the signal path: n Operate: allows normal transparent operation of the element. n Scan Load/Shift: used to serially load/shift data into the scan chain while simultaneously unloading the last sample. n Scan Data Apply: allows the scan element to control the value of the output, thereby controlling the logic driven by Q. n Scan Sample: gives observability of logic that fans into the scan element. n Scan cell provides observability and controllability of the signal path: n Operate: allows normal transparent operation of the element. n Scan Load/Shift: used to serially load/shift data into the scan chain while simultaneously unloading the last sample. n Scan Data Apply: allows the scan element to control the value of the output, thereby controlling the logic driven by Q. n Scan Sample: gives observability of logic that fans into the scan element.

1-56 Scan Test Timing

1-57 Multiple Scan Chains

1-58 Multiple Scan Chains Using multiple scan chains: Reduces required tester memory per channel Reduces test application time

1-59 Stuck-At Scan Diagnostics

1-60 Scan Testing Methodology n Advantages Direct Controllability & Observability of Internal Nodes Enables Combinational ATPG More Efficient Vectors Higher Potential Fault Coverage Deterministic Quality Metric Efficient Diagnostic Capability AC and DC Compliance n Concerns Power Consumption Clock Skew Design Rule Impact on Budgets n Advantages Direct Controllability & Observability of Internal Nodes Enables Combinational ATPG More Efficient Vectors Higher Potential Fault Coverage Deterministic Quality Metric Efficient Diagnostic Capability AC and DC Compliance n Concerns Power Consumption Clock Skew Design Rule Impact on Budgets

1-61 Boundary Scan Architecture

1-62 Built-In Self Test (BIST) n BIST is the capability of a circuit (chip, board, system) to test itself. n BIST architectures consist of Test pattern generators (TPGs) Output response analyzers (ORAs) Circuit under test (CUT) Distribution system for transmitting data from TPGs to CUTs and from CUTs to ORAs BIST controller n BIST is the capability of a circuit (chip, board, system) to test itself. n BIST architectures consist of Test pattern generators (TPGs) Output response analyzers (ORAs) Circuit under test (CUT) Distribution system for transmitting data from TPGs to CUTs and from CUTs to ORAs BIST controller

1-63 Built-In Self Test Example

1-64 Advantages of BIST n Fast, efficient and hierarchical - same hardware is capable of testing chips, boards and systems. n No need of expensive ATE (cost >= $10 milion) n Testing during operation and maintenance n Uniform technique for production, system and maintenance tests n Dynamic properties of the circuit can be tested at speed n Can be used for delay testing as it can be used in real time n Fast, efficient and hierarchical - same hardware is capable of testing chips, boards and systems. n No need of expensive ATE (cost >= $10 milion) n Testing during operation and maintenance n Uniform technique for production, system and maintenance tests n Dynamic properties of the circuit can be tested at speed n Can be used for delay testing as it can be used in real time

1-65 ConclusionConclusion n With increasing design complexity, testing cost has increased dramatically. n Testing must be addressed early in the design process. n Design engineers must have good testing and design for testability knowledge. n Testing introduced in Computer & Electrical Engineering Curriculum in many universities COE 464: Testing of Digital Circuits COE 571: Digital System Testing n With increasing design complexity, testing cost has increased dramatically. n Testing must be addressed early in the design process. n Design engineers must have good testing and design for testability knowledge. n Testing introduced in Computer & Electrical Engineering Curriculum in many universities COE 464: Testing of Digital Circuits COE 571: Digital System Testing