Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration.

Slides:

Advertisements

Similar presentations

TDC130: High performance Time to Digital Converter in 130 nm

Advertisements

Konstantin Stefanov, Rutherford Appleton Laboratory4 th ECFA-DESY Workshop, 1-4 April 2003p. 1 CCD-based Vertex Detector - LCFI status report Konstantin.

Vertex detector optimisation: status and strategies

1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory LCFI Status Report: Sensors for the ILC Konstantin Stefanov CCLRC Rutherford Appleton Laboratory.

The Status of the LCFI Project Snowmass 2005 Joel Goldstein CCLRC Rutherford Appleton Laboratory For the LCFI Collaboration.

A CCD-based vertex detector Status report from the LCFI collaboration

Konstantin Stefanov, Rutherford Appleton Laboratory UTA LC Workshop, 8 Jan Report from the LCFI collaboration Konstantin Stefanov RAL Introduction:

1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 1 26 September 2006 LCFI Status Report: Vertex Detector R&D Konstantin Stefanov CCLRC Rutherford.

January US LC Workshop SLAC – Chris Damerell 1 Strategies for pickup and noise suppression with different vertex detector technologies Chris Damerell.

LCFI Collaboration Status Report LCWS 2004 Paris Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, RAL.

ISIS and SPiDeR Zhige ZHANG STFC Rutherford Appleton Laboratory.

Advanced Implantation Detector Array (AIDA): Update & Issues Tom Davinson School of Physics & Astronomy The University of Edinburgh presented by Tom Davinson.

The group is developing readout electronics for initial use with the prototype test-stand at Fermilab. This work will contribute towards the design and.

Results from first tests of TRD prototypes for CBM DPG Frühjahrstagung Münster 2011 Pascal Dillenseger Institut für Kernphysik Frankfurt am Main.

HIPPO, a Flexible Front-End Signal Processor for High-Speed Image Sensor Readout Carl Grace, Dario Gnani, Jean-Pierre Walder, and Bob Zheng June 10, 2011.

M. Szelezniak1PXL Sensor and RDO review – 06/23/2010 STAR PXL Sensors Overview.

SKIROC New generation readout chip for ECAL M. Bouchel, J. Fleury, C. de La Taille, G. Martin-Chassard, L. Raux, IN2P3/LAL Orsay J. Lecoq, G. Bohner S.

Andrei Nomerotski 1 CCD-based Pixel Detectors by LCFI Andrei Nomerotski (U.Oxford) on behalf of LCFI collaboration Hiroshima2006, Carmel CA Outline  LCFI.

Andrei Nomerotski 1 External Electronics : WP4 Andrei Nomerotski, LCFI Collaboration Meeting 28 March 2006 Outline  Test Boards for Sensors : MotherBoards.

Vertex 2002, Kona, Hawaii S.Xella – Rutherford Appleton Laboratory A vertex detector for the next linear collider Stefania Xella on behalf of the LCFI.

19 March 2005 LCWS 05 M. Breidenbach 1 SiD Electronic Concepts SLAC –D. Freytag –G. Haller –J. Deng –mb Oregon –J. Brau –R. Frey –D. Strom BNL –V. Radeka.

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Linear Collider Flavour Identification (LCFI)

A new idea of the vertex detector for ILC Y. Sugimoto Nov

Development of Readout ASIC for FPCCD Vertex Detector 01 October 2009 Kennosuke.Itagaki Tohoku University.

Nicolo de Groot, Rutherford Appleton LaboratoryDESY PRC, 7/8 May 2003p. 1 CCD-based Vertex Detector - LCFI status report Nicolo de Groot RAL/Bristol Conceptual.

Fine Pixel CCD Option for the ILC Vertex Detector

July US LC Workshop Cornell U – Chris Damerell 1 A CCD-based vertex detector Chris Damerell on behalf of the LCFI Collaboration Project overview.

LCFI Collaboration Status Report LCUK Meeting Oxford, 29/1/2004 Joel Goldstein for the LCFI Collaboration Bristol, Lancaster, Liverpool, Oxford, QMUL,

Pixel hybrid status & issues Outline Pixel hybrid overview ALICE1 readout chip Readout options at PHENIX Other issues Plans and activities K. Tanida (RIKEN)

27 th September 2007AIDA design meeting. 27 th September 2007AIDA design meeting.

Front End Circuit.. CZT FRONT END ELECTRONICS INTERFACE CZTASIC FRONT END ELECTRONICS TO PROCESSING ELECTRONICS -500 V BIAS+/-2V +/-15V I/O signal.

Development of an ASIC for reading out CCDS at the vertex detector of the International Linear Collider Presenter: Peter Murray ASIC Design Group Science.

Vertex Detector for GLD 3 Mar Y. Sugimoto KEK.

VIP1: a 3D Integrated Circuit for Pixel Applications in High Energy Physics Jim Hoff*, Grzegorz Deptuch, Tom Zimmerman, Ray Yarema - Fermilab *

1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory 1 ECFA 2006, Valencia LCFI Status Report: Vertex Detector R&D Konstantin Stefanov CCLRC Rutherford.

Fine Pixel CCD for ILC Vertex Detector ‘08 7/31 Y. Takubo (Tohoku U.) for ILC-FPCCD vertex group ILC vertex detector Fine Pixel CCD (FPCCD) Test-sample.

J. Crooks STFC Rutherford Appleton Laboratory

Joel Goldstein, RAL 4th ECFA/DESY LC Workshop, 1/4/ Vertex Readout Joel Goldstein PPd, RAL 4 th ECFA/DESY LC Workshop DAQ Session 1 st April 2003.

FPCCD Vertex detector 22 Dec Y. Sugimoto KEK.

1 Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory LCFI Detector R&D Status Report WP2 – Sensor Development WP3 – Readout and Drive Electronics.

Andrei Nomerotski 1 Andrei Nomerotski, University of Oxford for LCFI collaboration ILC VD Workshop, Menaggio, 23 April 2008 LCFI Report.

BTeV Hybrid Pixels David Christian Fermilab July 10, 2006.

Konstantin Stefanov, CCLRC Rutherford Appleton Laboratory PPRP open session: LCFI, IoP, 8 th September Linear Collider Flavour Identification (LCFI)

LCFI meeting 19 th August 2008 TESTING OF CPR2A Mirek Havranek, Peter Murray, Konstantin Stefanov, Stephen Thomas.

CMOS MAPS with pixel level sparsification and time stamping capabilities for applications at the ILC Gianluca Traversi 1,2

1 FPCCD VTX Work Plan Y. Sugimoto 2010/1/22. 2 FPCCD: Features and R&D issues (1/2) Small pixel size (~5  m) –Sensor development Small size chip; ~6mm.

1 Konstantin Stefanov, STFC Rutherford Appleton Laboratory 1 TILC08, Sendai, Japan A CCD Based Vertex Detector Konstantin Stefanov STFC Rutherford Appleton.

CMS Pixels: Fermilab Farah Fahim, Gregory Deptuch, Jim Hoff, Alpana Shenai, Marcel Trimpl.

Pixel detector development: sensor

Scott Mandry, EUDET JRA1 Meeting, DESY 30 th January ISIS1 Testbeam EUDET JRA1 Meeting, DESY 30 th January 2008 Scott Mandry LCFI Collaboration.

Eleuterio SpiritiILC Vertex Workshop, April On pixel sparsification architecture in 130nm STM technology ILC Vertex Workshop April 2008 Villa.

M. TWEPP071 MAPS read-out electronics for Vertex Detectors (ILC) A low power and low signal 4 bit 50 MS/s double sampling pipelined ADC M.

FPCCD VTX Work Plan Y. Sugimoto 2010/1/22. FPCCD: Features and R&D issues (1/2) Small pixel size (~5  m) –Sensor development Small size; ~6mm x 6mm Full.

1 Konstantin Stefanov, Rutherford Appleton Laboratory 1 LCWS2007 Progress with the CPCCD and the ISIS Konstantin Stefanov Rutherford Appleton Laboratory.

1 Konstantin Stefanov, STFC Rutherford Appleton Laboratory 1 Vertex 2007, Lake Placid A CCD Based Vertex Detector Konstantin Stefanov STFC Rutherford Appleton.

ASIC Development for Vertex Detector ’07 6/14 Y. Takubo (Tohoku university)

Aurore Savoy-Navarro 1), Albert Comerma 2), E. Deumens 3), Thanh Hung Pham 1), Rachid Sefri 1) 1) LPNHE-Université Pierre et Marie Curie/IN2P3-CNRS, Fr.

Sonja Hillert, University of Oxford2 nd ECFA LC workshop, Durham, 1 st September 2004 p. 0 Recent results from R&D towards a vertex detector at the international.

SKIROC status CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007 Presented by Julien Fleury.

FEE for Muon System (Range System) Status & Plans G.Alexeev on behalf of Dubna group Turin, 16 June, 2009.

FPGA based signal processing for the LHCb Vertex detector and Silicon Tracker Guido Haefeli EPFL, Lausanne Vertex 2005 November 7-11, 2005 Chuzenji Lake,

Andrei Nomerotski 1 Andrei Nomerotski, University of Oxford for LCFI collaboration LCWS2008, 17 November 2008 Column Parallel CCD and Raw Charge Storage.

LCFI Detector Overview

ECAL front-end electronic status

Silicon Pixel Detector for the PHENIX experiment at the BNL RHIC

A 3D deep n-well CMOS MAPS for the ILC vertex detector

LCFI Status Report: Sensors for the ILC

SiD Electronic Concepts

TPC electronics Atsushi Taketani

SKIROC status CERN – CALICE/EUDET electronic & DAQ meeting – 22/03/2007 Presented by Julien Fleury.

Presentation transcript:

Latest Developments from the CCD Front End LCWS 2005 Stanford Joel Goldstein, RAL for the LCFI Collaboration

Joel Goldstein, RALLCWS 3/05 2 Outline 1.Reminder: ILC Vertex Detector Column Parallel CCDs Conceptual Readout Scheme 2.First Generation Prototypes 3.Second Generation Prototypes

Joel Goldstein, RALLCWS 3/05 3 The Vertex Detector 5 layers (15-60mm) ~ 0.1% X 0 per layer 20 m 20 m pixels 800 million channels Background rates force readout –50 s for Layer 1 –250 s for Layer 2

Joel Goldstein, RALLCWS 3/05 4 Column Parallel CCDs Separate readout for each column Readout ASIC bump-bonded to CCD ASICs contain amplifiers, ADC and digital processing N+ 1 Column Parallel CCD Readout time = (N+1)/F out

Joel Goldstein, RALLCWS 3/05 5 Ladder Readout Layer 1 read out 20 times per bunch train 50k z pixels Layers 2-5 read out 5 times per bunch train 31k z pixels 4.4 GPixels in total Have to sparsify at front end

Joel Goldstein, RALLCWS 3/05 6 Detector Level DAQ Amplification ADC Filtering Clustering Multiplexer

Joel Goldstein, RALLCWS 3/05 7 Front End Readout Chain 1.3 million hits = 20 Mbytes per bunch train

Joel Goldstein, RALLCWS 3/05 8 First Prototype CPC/CPR Column parallel CCD principle proven Noise < 100 electrons Minimum clock ~1.9 V No sparsification in ASIC Charge Amplifiers (inverting) Voltage Amplifiers (non-inverting) 6 keV X-rays

Joel Goldstein, RALLCWS 3/05 9 Next Generation ASIC No major changes to amplifiers or ADC Digital cluster finding: –2x2 kernel –Extended cluster read out Expanded cluster to be read out Cluster found

Joel Goldstein, RALLCWS 3/05 10 CPR-2 Output Sparsification Cluster Binary 5-bit ADC Preamp Input & Multiplexing Finding Conversion DATA

Joel Goldstein, RALLCWS 3/05 11 CPR-2 IBM 0.25 m 6 x 9.5 mm Chips have arrived at RAL Stand alone testing starting Test features: –direct analogue I/O pads –I/O serial register between ADCs and cluster logic

Joel Goldstein, RALLCWS 3/05 12 Summary First generation CPCCD/ASIC tested Second generation ASIC ready for testing Cluster finding implemented Sparsification at front end –Major steps on road to ILC readout