Instruction Set Architecture Basics

Our Progress Done with levels 0 and 1 Seen multiple examples of level 2 Ready for ISA general principles

Choices, choices ISA design is a balancing act – Hardware complexity – Compiler complexity – Programmer friendliness – Backwards compatibility

Choice 1 : Memory Model Memory Model – How big is a word? – Is main memory byte addressable? Word addressable? – How does access have to be aligned?

Choice 1 : Memory Model Memory Model – Is the machine little endian or big endian? -16 (FFFFFFF0) followed by 5 ( ) Which is easier to find sign? Which is easier to convert int to char? Big Endian FF F Little Endian FF F000 05

Choice 1 : Memory Model Memory Model – Is the machine little endian or big endian? "Compute" Which is easier for programmers to read? Big Endian Compute\0 Little Endian pmoC\0etu

Who uses what? MARS is little endian – MIPS hardware is biendian

Choice 2 : CPU Storage How will CPU store data? – Accumulator – Stack – General Purpose Registers

Choice 2 : CPU Storage Accumulator architecture – MARIE / Little Man Computer – Shorter instructions Add X vs Add $9, $8, $7 – More fiddly to program

Choice 2 : CPU Storage Stack based CPU storage – Loads place value on stack – Math operations pop top two values, work with them, push answer – Store pops value off stack

Choice 2 : CPU Storage Java bytecode is stack based language: Pro/Con + Instruction Size + Hardware neutrality - Ease of development - Possibly lots of memory access

Choice 2 : CPU Storage General Purpose Registers – Most common approach – Pro/Con - Longer instructions : ADD $9, $8, $7 + Registers faster than memory + Easier to program

Choice 2 : CPU Storage General Purpose Registers – How restricted are we to registers? Memory-Memory (Older machines) – Can work directly with memory in all instructions Register-Memory (Intel) – At least one operand in register, other can be directly from memory Load-Store (MIPS) – Only special load/store instructions can reference memory More Flexible More Complex

Choice 3 : Instruction Length Will instructions be – Fixed length MIPS / MARIE Easier to decode – Variable length Intel Better use of space

Choice 4 : Number of Operands How many operands will instructions be allowed to have? – 0 : Opcode only Halt / nop / stack based add – 1 : Usually memory address / immediate Load X (MARIE) / j end (MIPS) – 2 : Registers, memory or immediates Move $9, $8 / li $8, 100 – 3 : Registers, memory or immediates Add $9, $8, $7 Longer, More flexible Instructions

Examples 3 Operand Instructions: Z = X  Y + W  U MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 R1 R2

Examples 3 Operand Instructions: Z = X  Y + W  U MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 R1X*Y R2

Examples 3 Operand Instructions: Z = X  Y + W  U MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 R1X*Y R2W*U

Examples 3 Operand Instructions: Z = X  Y + W  U MULT R1,X,Y MULT R2,W,U ADD Z,R1,R2 R1X*Y R2W*U 5 trips to main memory… may be able to do pairs at same time

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X R2

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X*Y R2 Destination always same as first operand

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X*Y R2W

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X*Y R2W*U Destination always same as first operand

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X*Y + W*U R2W*U Destination always same as first operand

Examples 2 Operand Instructions: Z = X  Y + W  U LOAD R1,X MULT R1,Y LOAD R2,W MULT R2,U ADD R1,R2 STORE Z,R1 R1X*Y + W*U R2W*U 5 trips to main memory

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX Destination assumed to be accumulator

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX*Y Destination assumed to be accumulator

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACX*Y tempX*Y

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW tempX*Y

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U tempX*Y

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U + X*Y tempX*Y

Examples 1 Operand Instructions - Accumulator Z = X  Y + W  U LOAD X MULT Y STORE TEMP LOAD W MULT U ADD TEMP STORE Z ACW*U + X*Y tempX*Y 7 trips to main memory

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z X Destination assumed to be top of stack

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z Y X Destination assumed to be top of stack

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z X * Y Take off top two items, multiply, put result back on stack

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W X * Y

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z U W X * Y

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W * U X * Y Take off top two items, multiply, put result back on stack

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z W * U + X * Y Take off top two items, add, put result back on stack

Examples 1 Operand Instructions – Stack based Z = X  Y + W  U PUSH X PUSH Y MULT PUSH W PUSH U MULT ADD STORE Z trips to main memory (Mult/Add 2 or 3 each!)

Choice 5 : Expanding Opcodes Fixed opcode : set length for instruction

Choice 5 : Expanding Opcodes Expanding Opcode : – Different instructions different length opcodes Pro/Cons: + More efficient use of space - Harder to decode

Expanding Opcode Expanding Opcode : – Special opcode means : keep reading

Expanding Opcode Expanding Opcode : – Special opcode

Construction Example Example: Given 8-bit instructions is it possible to allow the following to be encoded? –3 instructions with two 3-bit operands. –2 instructions with one 4-bit operand. –4 instructions with one 3-bit operand.

Construction Example Example: Given 8-bit instructions is it possible to allow the following to be encoded? –3 instructions with two 3-bit operands. –2 instructions with one 4-bit operand. –4 instructions with one 3-bit operand. 8 bits = 256 patterns How many patterns are needed?

Construction Example An instruction with two 3-bit operands –2 3 possible values for Xs –2 3 possible values for Ys –2 3 x 2 3 = 2 6 = 64 patterns XXXYYY

Construction Example An instruction with two 3-bit operands –2 3 x 2 3 = 2 6 = 64 patterns –Need three of these: 3 x 64 = 192 different patterns XXXYYY 00XXXYYY 01XXXYYY 10XXXYYY

Construction Example Example: Given 8-bit instructions is it possible to allow the following to be encoded? –3 instructions with two 3-bit operands. –2 instructions with one 4-bit operand. –4 instructions with one 3-bit operand. 3  2 3  2 3 = 192 patterns for the two 3-bit operands 2  2 4 = 32 patterns for the 4-bit operands 4  2 3 = 32 patterns for the 3-bit operands. We need: Total: 256 patterns… we can do that

Construction Example Start with our 3 - two 2-bit operand instructions:

Construction Example Need 2 bit escape code to indicate longer opcode

Construction Example Need two 4-bit operand instructions and escape pattern – 2 bits to select either 4-bit instruction or escape

Construction Example 111… Indicates a 5 bit long opcode Have room for four 3-bit instructions