CPS3340 COMPUTER ARCHITECTURE Fall Semester, 2013 09/10/2013 Lecture 5: Combinational Logic Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE.

Slides:



Advertisements
Similar presentations
Random-Access Memory (RAM)
Advertisements

Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Chapter 3 – Combinational.
1 KU College of Engineering Elec 204: Digital Systems Design Lecture 9 Programmable Configurations Read Only Memory (ROM) – –a fixed array of AND gates.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /23/2013 Lecture 7: Computer Clock & Memory Elements Instructor: Ashraf Yaseen DEPARTMENT OF MATH &
CPEN Digital System Design
Documentation Standards Programmable Logic Devices Decoders
Parity. 2 Datasheets TTL:  CMOS: 
Chapter 6 – Selected Design Topics Part 4 – Programmable Implementation Technologies Logic and Computer Design Fundamentals.
EE365 Adv. Digital Circuit Design Clarkson University Lecture #7 Intro to MSI PLDs and Decoders.
MOHD. YAMANI IDRIS/ NOORZAILY MOHAMED NOOR 1 Combinational Circuit – MSI Circuit ENCODER With the aid of K-map (don’t care situation), we can get D 0 =
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 – Selected Design Topics Part 4 – Programmable.

Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Chapter 3 – Combinational.
Multiplexers, Decoders, and Programmable Logic Devices
ECE 331 – Digital System Design Tristate Buffers, Read-Only Memories and Programmable Logic Devices (Lecture #16) The slides included herein were taken.
ECE 301 – Digital Electronics
Digital Logic Design Lecture 18. Announcements HW 6 up on webpage, due on Thursday, 11/6.
TDC 311 Digital Logic. Truth Tables  AND  OR  NOT  NAND  NOR  XOR  XNOR.
طراحی مدارهای منطقی نیمسال دوم دانشگاه آزاد اسلامی واحد پرند.
Charles Kime & Thomas Kaminski © 2004 Pearson Education, Inc. Terms of Use (Hyperlinks are active in View Show mode) Terms of Use Lecture 13 – Programmable.
9/20/6Lecture 3 - Instruction Set - Al1 Address Decoding for Memory and I/O.
CS 1308 – Computer Literacy and the Internet. It’s Not Magic  The goal of the next series of lectures is to show you exactly how a computer works. 
Random-Access Memory (RAM)
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Hao Ji.
Chapter 4 The Building Blocks: Binary Numbers, Boolean Logic, and Gates.
Transistors and Logic Circuits. Transistor control voltage in voltage out control high allows current to flow -- switch is closed (on) control low stops.
Memory and Programmable Logic Dr. Ashraf Armoush © 2010 Dr. Ashraf Armoush.
Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 6 – Selected Design Topics Part 4 – Programmable.
1 DIGITAL ELECTRONICS. 2 OVERVIEW –electronic circuits capable of carrying out logical (boolean) and arithmetic operations on information stored as binary.
CSET 4650 Field Programmable Logic Devices
ROM & PLA Digital Logic And Computer Design
1 Lecture #7 EGR 277 – Digital Logic Reading Assignment: Chapter 4 in Digital Design, 3 rd Edition by Mano Chapter 4 – Combinational Logic Circuits A)
Chapter
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /05/2013 Lecture 4: Basics of Logic Design Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER.
Princess Sumaya University
Integrated Circuits. Integrated Circuit (IC) A silicon crystal (chip) containing electronic components that create the logic gates we’ve been looking.
Memory 10/27/081ECE Lecture. Memory Memory Types Using memory to implement logic functions 10/27/082ECE Lecture.
Fall 2004EE 3563 Digital Systems Design EE 3563 Combinational Design Practices  Change in reading assignment: 5.3.1,  SSI – Small Scale Integration.
Computer logic Data and programs in digital computers are represented and processed by electronic circuit networks called digital logic circuits or logic.
CS 1308 – Computer Literacy and the Internet Building the CPU.
CPS3340 COMPUTER ARCHITECTURE Fall Semester, /3/2013 Lecture 9: Memory Unit Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL.
CPS3340 Computer Architecture Fall Semester, 2013
CS/COE0447 Computer Organization & Assembly Language
Appendix C Basics of Digital Logic Part I. Florida A & M University - Department of Computer and Information Sciences Modern Computer Digital electronics.
IC design options PLD (programmable logic device)
1 EE121 John Wakerly Lecture #5 Documentation Standards Programmable Logic Devices Decoders.
Lecture 24: 12/3/2002CS170 Fall CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University.
CS151 Introduction to Digital Design Chapter 3: Combinational Logic Design 3-5 Combinational Functional Blocks 3-6 Rudimentary Logic Functions 3-7 Decoding.
LECTURE 4 Logic Design. LOGIC DESIGN We already know that the language of the machine is binary – that is, sequences of 1’s and 0’s. But why is this?
COMPUTER ARCHITECTURE & OPERATIONS I Instructor: Yaohang Li.
Lecture 23: 11/26/2002CS170 Fall CS170 Computer Organization and Architecture I Ayman Abdel-Hamid Department of Computer Science Old Dominion University.
1 CS/COE0447 Computer Organization & Assembly Language Logic Design Appendix C.
Programmable Logic Devices
Gunjeet Kaur Dronacharya Group of Institutions. Outline Introduction Random-Access Memory Memory Decoding Error Detection and Correction Programmable.
Appendix C Basics of Logic Design. Appendix C — Logic Basic — 2 Logic Design Basics §4.2 Logic Design Conventions Objective: To understand how to build.
Chapter- 9 Programmable Logic Devices DHADUK ANKITA ENRL NO Noble Engineering College- Junagadh.
Computer Architecture & Operations I
Computer Architecture & Operations I
Morgan Kaufmann Publishers
Logic Devices. Decoder 2-to-4 Decoder 3-to-8 Decoder.
Transistors and Logic Circuits
Computer Architecture & Operations I
Computer Architecture & Operations I
Logic and Computer Design Fundamentals
ECE 434 Advanced Digital System L03
ECE434a Advanced Digital Systems L02
Programmable Configurations
Part I Background and Motivation
COMS 361 Computer Organization
1.Introduction to Advanced Digital Design (14 marks)
Presentation transcript:

CPS3340 COMPUTER ARCHITECTURE Fall Semester, /10/2013 Lecture 5: Combinational Logic Instructor: Ashraf Yaseen DEPARTMENT OF MATH & COMPUTER SCIENCE CENTRAL STATE UNIVERSITY, WILBERFORCE, OH 1

Review  Last Class  Basic of Logic Design  This Class  Integrated Circuits  Decoder  Multiplexor  PLA  ROM  Don’t Care  Bus  Next Class  Design of ALU

Integrated Circuit  Integrated Circuit (IC)  A small electronic device made out of a semiconductor material  Classifications  SSI (small-scale integration) up to 100 electronic components per chip  MSI (medium-scale integration) 100~3,000 electronic components per chip  LSI (large-scale integration) 3,000~100,000 electronic components per chip  VLSI (very large-scale integration) 100,0000 to 1,000,0000 electronic components per chip  ULSI (ultra large-scale integration) More than 1 million electronic components per chip

Decoder  Decoder  A logic block that has n-bit input and 2 n outputs, where only one output is asserted for each input combination  If the input is i (in binary), then output i is 1 others are 0

Decoder Example  3-8 Decoder

Multiplexor  Multiplexor  A selector The output is selected by an input control

Implementation of a Multiplexor

n-input Multiplexor  A Multiplexor can have n-inputs  Require selective inputs  Implementation of an n-input Multiplexor

Two-level Logic  Try to Remember: Any Boolean Logic function can be implemented with only NOT, AND, OR functions  We can also find that all logic functions can be written in a canonical form, in 2 levels  Sum of Product Logical Sum (OR) of terms joined by Product (AND)  Product of Sum Logical Product (AND) of terms joined by Sum (OR)

Example  Consider a logic function  Equivalent to sum of products  Equivalent to product of sums

In Class Exercise  Considering the following truth table for D, write the function of D using sum of products

Answer  Combinations that D is 1  Answer

Programmable Logic Array  Programmable Logic Array (PLA)  Two stages of logic An array of AND gates (product terms) An array of OR gates

PLA Example  Considering the following table, implement the PLA for D, E, F

PLA Example – cont.  A PLA can directly implement the truth table of a set of logic functions with multiple inputs and outputs.  Each entry where the output is true requires a product term  there will be a corresponding row in the PLA  Each output corresponds to a potential row of OR gates in the second stage 15

Another PLA Representation  Dot in the AND plane  Input, or its inverse, occurs in the product term  Dot in the OR plane  Corresponding product term appears in the corresponding output

Read Only Memory  Read Only Memory (ROM)  Has a set of locations that can be read  Contents of these locations are fixed  Programmable ROM (PROM)  Can be burnt using a device called a “ROM programmer”  Erasable Programmable Read Only Memory (EPROM)  Data in the ROM can be deleted under ultra-violet rays  EEPROM (Electrically Erasable Read Only Memory)  Data in the ROM can be erased by a simple electric current

ROM  Height  m inputs  2 m addressable entries (input lines)  Width  n outputs (functions)  2 n output bits  mxn is the shape of the ROM

ROMs and PLAs  PLA is partially decoded  ROM is fully decoded  Contains a full output word for every possible input combination  Always contain more entries than PLA PLA (7 entries) ROM (8 entries – 1 unused)

Don’t Care  Don’t Care  We don’t care about the actual values  Output Don’t Care  We don’t care about the value of an output for some input combination  Input Don’t Care  An output only depends on some of the inputs  Advantages of Don’t Care  Easier to optimize the implementation of a logic function

Example of Don’t Cares  Original Truth Table

Example of Don’t Cares  Output Don’t Cares  Input Don’t Cares

Array of Logic Elements  Bus  In logic design, a collection of data lines that is treated together as a single logical signal  Shared collection of lines with multiple sources 32-bit wide 2-to-1 multiplexor

Summary  Integrated Circuits  Decoder  Multiplexor  PLA  ROM  Don’t Care  Bus

What I want you to do  Review Chapter 1