CSE477 L28 DFT.1Irwin&Vijay, PSU, 2003 CSE477 VLSI Digital Circuits Fall 2003 Lecture 28: Design for Test Mary Jane Irwin ( ) [Adapted from Rabaey’s Digital Integrated Circuits, Second Edition, ©2003 J. Rabaey, A. Chandrakasan, B. Nikolic]

CSE477 L28 DFT.2Irwin&Vijay, PSU, 2003 Test Procedures  Diagnostic test l used in debugging and defect localization l can afford to spend time testing  Production test - “go/no go” l used in chip production (wafer and/or packaged) l since have to test each part, must be fast  Parametric test l [v, i] versus [0,1] l check parameters such as noise margins, V t, t p at corners (range of temperatures and supply voltage variations) l usually done with special wafer drop-ins

CSE477 L28 DFT.3Irwin&Vijay, PSU, 2003 Testing Fabricated Designs  Goals of design-for-test (DFT) l make testing of manufactured parts swift and comprehensive  DFT mantra l Provide controllability and observability  Components of DFT strategy l Provide test patterns that guarantee reasonable coverage l Provide circuitry to enable testing

CSE477 L28 DFT.4Irwin&Vijay, PSU, 2003 Two Important Test Properties  Controllability - measures the ease of bringing a node to a given condition using only the input pins  Observability - measures the ease of observing the value of a node at the output pins  Need both! l combinational circuits are both - so relatively easy to determine test patterns l state in sequential circuits problematic - so turn into a combinational circuit (or use self-test)

CSE477 L28 DFT.5Irwin&Vijay, PSU, 2003 Generating and Validating Test Vectors  Automatic test-pattern generation (ATPG) l for given fault, determine excitation vector (called test vector) that will propagate error to primary (observable) output l majority of available tools: combinational networks only l sequential ATPG available from academic research  Fault simulation l determines test coverage of proposed test-vector set l simulates correct network in parallel with faulty networks  Both require adequate models of faults in CMOS integrated circuits

CSE477 L28 DFT.6Irwin&Vijay, PSU, 2003 Fault Models Stuck-at models sa0 - stuck at zero (short-circuit to GND) sa1 - stuck at one (short-circuit to V dd ) A B C Z   

CSE477 L28 DFT.7Irwin&Vijay, PSU, 2003 Fault Models Stuck-at models sa0 - stuck at zero (short-circuit to GND) sa1 - stuck at one (short-circuit to V dd ) A B C Z     - A sa1  - A sa0 or B sa0  - C sa1 or Z sa0

CSE477 L28 DFT.8Irwin&Vijay, PSU, 2003 Problem with Stuck-at Model  A B BA Z A B Z

CSE477 L28 DFT.9Irwin&Vijay, PSU, 2003 Problem with Stuck-at Model sequential effect - needs two vectors to ensure detection  A B BA Z A B Z Z i-1 output node floats (retains old value)

CSE477 L28 DFT.10Irwin&Vijay, PSU, 2003 Path Sensitization  Determine the input pattern that makes a fault controllable (triggers the fault) and observable (makes its impact visible at the output nodes) A B C D E U X Y Z sa0 Controllable: Observable:

CSE477 L28 DFT.11Irwin&Vijay, PSU, 2003 Path Sensitization  Determine the input pattern that makes a fault controllable (triggers the fault) and observable (makes its impact visible at the output nodes) A B C D E U X Y Z sa0 Controllable: Observable: Try to set U to 1  A = 1 and B = 1 Propagate U to Z  X = 1 and E =

CSE477 L28 DFT.12Irwin&Vijay, PSU, 2003 Test Problem Size comb logic module N inputs K outputs 2 N input patterns comb logic module N inputs K outputs 2 N+M input patterns M state regs

CSE477 L28 DFT.13Irwin&Vijay, PSU, 2003 Test Problem Size comb logic module N inputs K outputs 2 N input patterns comb logic module N inputs K outputs 2 N+M input patterns M state regs N=20  1 million patterns 1  sec/pattern  1 second test N=20, M=10  1 billion patterns 1  sec/pattern  16 minute test

CSE477 L28 DFT.14Irwin&Vijay, PSU, 2003 Reducing Number of Test Vectors  Two features can be exploited to reduce the number of test vectors  Redundancy - a single fault in the circuit is usually covered by several input patterns; detection of the fault requires only one  Reduced fault coverage - relax the requirement that all faults be detected (95% to 99% fault coverage is typical)

CSE477 L28 DFT.15Irwin&Vijay, PSU, 2003 Test Approaches  Scan based test  Self test  Ad-hoc testing Problem is getting harder l increasing complexity and heterogeneous combination of modules in system-on-a-chip. l advanced packaging and assembly techniques extend problem to the board level

CSE477 L28 DFT.16Irwin&Vijay, PSU, 2003 Scan Based Test Comb logic A regAregA Comb logic B regBregB InOut ScaninScanout Two operational modes normal mode (N-bit wide clocked registers) test mode (registers chained as a single serial shift register) run  test  run  test 

CSE477 L28 DFT.17Irwin&Vijay, PSU, 2003 Scan Path FF Implementation Q (& scanout) D QMQM run  scanin test 

CSE477 L28 DFT.18Irwin&Vijay, PSU, 2003 Polarity Hold Shift FF flipflop latch Q system data !Q scanout !scanout run  scanin testA  testB  Introduced at IBM and set as company policy for all designs

CSE477 L28 DFT.19Irwin&Vijay, PSU, 2003 Scan Register FF Test !Test Test In 0 Out 0 Scanin FF Test !Test Test In 1 Out 1 FF Test !Test Test In 2 Out 2 FF Test !Test Test In 3 Out 3 Scanout Test Clock N cycles scan in N cycles scan out 1 cycle evaluate

CSE477 L28 DFT.20Irwin&Vijay, PSU, 2003 Scan Path Testing Partial scan can be more effective for pipelined datapaths REG[5] REG[4] REG[3]REG[2] REG[0]REG[1] COMP OUT SCANIN COMPIN SCANOUT AB

CSE477 L28 DFT.21Irwin&Vijay, PSU, 2003 Boundary Scan (JTAG) Board testing becoming as problematic as chip testing

CSE477 L28 DFT.22Irwin&Vijay, PSU, 2003 Built in Self Test (BIST)  The circuit decides if the results are correct!  Need a way to supply test patterns (stimulus generator) and to compare the circuit’s responses to a known correct sequence (response analyzer) (Sub)circuit under test Stimulus generator Response analyzer Test controller

CSE477 L28 DFT.23Irwin&Vijay, PSU, 2003 Stimulus Generator (LRSR) A1A1 A2A2 A3A3 Pseudo-random pattern generator A0A

CSE477 L28 DFT.24Irwin&Vijay, PSU, 2003 Response Analyzer Counter Latch In Counts the number of 0  1 and 1  0 transitions Counter value (signature of the circuit) is then compared to the known correct count Signature Analysis to comparison circuitry

CSE477 L28 DFT.25Irwin&Vijay, PSU, 2003 Response Analyzer Counter Latch In Counts the number of 0  1 and 1  0 transitions Counter value (signature of the circuit) is then compared to the known correct count Signature Analysis 0  0  1  0  1  0 0  1  0  1  0  0 0  1  1  1  1  0 to comparison circuitry 4

CSE477 L28 DFT.26Irwin&Vijay, PSU, 2003 BILBO R In 0 S0S0 R S1S1 In 1 R In 2 S2S2 B0B0 B1B1 scanin scaniout B0B0 B1B1 Op Mode

CSE477 L28 DFT.27Irwin&Vijay, PSU, 2003 BILBO R In 0 S0S0 R S1S1 In 1 R In 2 S2S2 B0B0 B1B1 scanin scaniout B0B0 B1B1 Op Mode 1 1 Normal 0 0 Scan In 0 In 1 In sc !sc !S 0 !S 1

CSE477 L28 DFT.28Irwin&Vijay, PSU, 2003 BILBO R In 0 S0S0 R S1S1 In 1 R In 2 S2S2 B0B0 B1B1 scanin scaniout B0B0 B1B1 Op Mode 1 1 Normal 0 0 Scan 1 0 BIST 0 1 Reset In 0 In 1 In sc !sc !S 0 !S 1 In i  !S i-1

CSE477 L28 DFT.29Irwin&Vijay, PSU, 2003 Use of BILBO Comb logic A BILBO A Comb logic B InOut seedinScanout Reg A is a BILBO register doing pattern generation to test Comb logic A run  test  Reg B is a BILBO register doing signature analysis to test Comb logic A BILBO B run  test 

CSE477 L28 DFT.30Irwin&Vijay, PSU, 2003 Ad-Hoc Test Inserting multiplexer improves testability I/O bus data Memory Processor address I/O bus data Memory Processor address test select

CSE477 L28 DFT.31Irwin&Vijay, PSU, 2003 Memory Self Test FSM Memory Under Test Signature Analysis data_in address & R/W control data_out Patterns: Writing/Reading 0s, 1s, Walking 0s, 1s Galloping 0s, 1s