Work Package 2: ASIC building blocks for SLHC ACEOLE Twelve Month Meeting 1 st October 2009 CERN – Geneva, Switzerland Paulo Moreira

Work Package 2 ACEOLE fellow (ESR): José Pedro Cardoso Associated partner: –INESC Porto / University of Porto –Visiting Scientist: Dr. Jose Machado da Silva CERN: –Work package leader: Paulo Moreira

ASIC Building Blocks for SLHC Development of Radiation-Hard ASIC building blocks –Low-Power, Low-Jitter VCXO based PLL Specifications Prototype development –Including design for testability and calibration Functional and electrical characterization Irradiation testing –Total Dose –Single Event Upsets Final ASIC and Macro-cell –Characterization –Documentation Technology: 130 nm CMOS –Low-noise 10 GHz VCO Specifications Modelling of radiation effects Development of a radiation robust circuits Integration of the macro-cell in the GBT10 ASIC Technology: 90 nm CMOS Training value: –ASIC design skills –Analogue and communication circuit design knowledge –Training on CAE tools for ASIC design –Involvement in the full ASIC design cycle: From specifications to production testing –Knowledge on radiation-tolerant design methodology –Design for testability methodologies –Training on radiation qualification tests procedures

On-the-job Training Theoretical foundations: –Study of oscillators Literature research (state of the art) Topologies: LC and XTAL Noise in oscillators CADENCE tools training: –Full cycle: From schematics to extracted simulations Integrated circuit design techniques: –Design and simulation (schematic and layout) of oscillators: Single-ended Differential

Training EPLF Course – “PLLs, VCOs and Frequency Synthesizers“ –29 th June to 1 st July 2009, EPFL, Lausanne, Switzerland ESSCIRC 2009 Conference –14-18 September 2009, Athens, Greece –Short course: "Nanoscale CMOS analog design from devices to system" PhD in Electrical and Computer Engineering –1st semester (2009/2010) Microelectronic and Micro-electro-Mechanical Technologies Test and Design for Testability Digital Communication Systems Seminars –2nd semester (2011/2012) Advanced Microelectronic Systems Design Instrumentation and Systems Testing Measure Theory and Stochastic Processes Individual Topics Conference paper submission(s) –2010 (at least one of the following): PRIME 2010 – July 2010 TWEPP 2010 – September 2010 DCIS 2010 – November 2010 –2010 (at least one of the following): IM3STW 2011– June 2011 DATE 2011– March 2011 ITC 2011– October 2011

Secondment Secondment will take place at: –INESC Porto, Portugal –University of Porto, Portugal PhD in Electrical and Computer Engineering –01/07/2009 to 26/02/2010 PhD studies –4 courses Design of XTAL based PLL –Jitter Measuring circuit –Automatic Amplitude Control/ Automatic Gain Control –Automatic Frequency Centering – 25/02/2011 to 29/07/2011 PhD studies –4 courses Design of a radiation tolerant LC VCO

Summary of Work 2 nd June, Pedro’s 1 st working day –Training on CAD tools –EPFL's Course report –Preparation and presentation of a short tutorial on the design of low phase-noise oscillators –Preliminary design and simulation of LC oscillators –Specification of the XTAL PLL ASIC

Training by Visiting Scientists Dr. Jose Machado da Silva –January 2010: “Analogue and mixed-signal testing and design for testability” (6 H) –September 2010: “Instrumentation and systems testing” (6 H) Contacts with teaching staff at UPorto are being held to organize further courses: –Possible topics: Reconfigurable digital systems Field programmable gate arrays Custom computing Advanced analogue and mixed-signal design

Milestones and Deliverables

Del. no. Titles of the Research Training Themes and description of deliverables and milestones Nature [1] [1] Dissemina tion level Delivery date [2] [2] Status TC21 Complete initial training courses (ASIC design, CAD tools, theory of phase-locked loops etc) n.a.6 Complete D21 Sign-off specification document for ASIC (IP block) RPublic6 Complete W2n Organize microelectronics user TWEPP workshop n.a.12,24,36 - M21 Tape out prototype design ready for submission ORestricted18 - D22 Completion of testing and irradiation of prototype ASIC with conference report or journal publication P + RPublic27 - M22 Tape out final ASIC design ready for submission ORestricted29 - D23 Complete testing/irradiation of final ASIC and system-level integration test. Final conference report and/or journal publication D + RPublic36 - [1] [1] The nature of the deliverable is coded as follows: R = Report, P = Prototype, D = Demonstrator, O = Other [2] [2] For research themes 1-5 the delivery dates are measured in months from the start of individual ESR contracts.