1. Follow-up meeting of the Administrative Agreement between FCT and CERN Vicente Leitão, Pedro (PH/ESE-ME, joined in May 2013) Supervisor: Moreira, Paulo November 5, 2014

2. Outline Radiation Hard Optical Link Project GBT Project Framework GBTX ASIC Project eCDR-PLL ASIC Project Further Work http://cern.ch/proj-gbt2p.leitao@cern.ch

3. Radiation Hard Optical Link Project – Aims to develop a radiation hard bi-directional optical link between on- detector and off-detector electronics – Can serve simultaneously applications such as data acquisition, timing, trigger and experimental control – It is divided in two parts: GBT chipset (radiation hard ASICs) and Versatile link optoelectonics components http://cern.ch/proj-gbt3p.leitao@cern.ch

4. GBT Project Framework – Stands for “Giga Bit Transceiver” (4.8 Gb/s bidirectional high-speed link) – GBT radiation-hard Chipset: GBTX ASIC GBLD (gigabit laser driver) ASIC GBTIA (gigabit trans-impedance amplifier) ASIC SCA (slow control adapter) ASIC eCDR-PLL (Clock-and-Data-Recovery and Phase-Locked-Loop) ASIC http://cern.ch/proj-gbt4p.leitao@cern.ch

5. GBTX ASIC Project GBTX ASIC Overview (in numbers) – High-speed data rate: 4.8 Gb/s – Design in 130 nm CMOS technology using radiation-hard techniques – ½ million gates – Custom flip-chip BGA 20x20 pin package = 200 pins – Onboard crystal – > 350x 8-bit configuration registers (All triplicated) Can be programmed through I2C Or through high-speed serial link – Up to 40 bidirectional e-links Differential lines – Data input, data output and clock output – Can work at 40/80/160/320 MHz and 80/160/320 Mb/s – 7 PLLs, 17 master DLL, 56 replica delay lines, 7 power domains, … – First prototypes arrived in June 2013 http://cern.ch/proj-gbt5p.leitao@cern.ch

6. GBTX ASIC Project GBTX ASIC Project summary (my work) – Preliminary functional tests using the IC tester – Functional validation and performance characterization using the Stand- Alone Test (SAT) board – Radiation tests campaigns using the SAT board Total Ionizing Dose, at CERN, Dec. 2013 Single Event Upsets, in Louvain-la-Nueve, Belgium, Feb. 2014 – Current: Production testing User support GBTX ASIC user application support – Results presented at TWEPP’14 Test Bench Development for the Radiation Hard GBTX ASIC – In the Topical workshop on electronics for particle physics, Aix-en-Provence, FR, Sept (2014) http://cern.ch/proj-gbt6p.leitao@cern.ch

7. GBTX ASIC Project Preliminary functional tests using the IC tester – Performed with an industrial IC tester at CERN CREDENCE Sapphire http://cern.ch/proj-gbt7p.leitao@cern.ch VHDL/Verilog representation of the ASIC Create/load the test vectors onto the IC tester Test vectors generated from the simulations Perform the test Validade the ASIC performance

8. GBTX ASIC Project Functional validation and performance characterization using the Stand-Alone Test (SAT) board http://cern.ch/proj-gbt8p.leitao@cern.ch

9. GBTX ASIC Project Functional validation and performance characterization using the Stand-Alone Test (SAT) board http://cern.ch/proj-gbt9p.leitao@cern.ch The total number of received frames, number of frame errors and bit errors; An histogram of the number of times a certain bit of the received frame was wrong; “SnapeShot” capability, logging up to 256 wrong frames, enabling to understand if a burst of errors occurred and where the errors are located inside the frame; Monitoring of internal GBTX registers; Power consumption monitoring; etc

10. GBTX ASIC Project Single Event Upsets, in Louvain-la-Neuve, Belgium, Feb. 2014 http://cern.ch/proj-gbt10p.leitao@cern.ch 22 Ne 7+ at θ = 0°, 30°, 45° and 60° 40 Ar 12+ at θ = 0°, 30°, 45° and 60° 58 Ni 18+ at θ = 0°, 30° and 45° 83 Kr 25+ at θ = 0°

11. GBTX ASIC Project Total Ionizing Dose, at CERN, Dec. 2013 X-rays up to 100 Mrad at 100 krad/s http://cern.ch/proj-gbt11p.leitao@cern.ch post-rad transmitter eye TJ = 85.28 ps (+7.7% pre-rad) RJ(rms,narrow) = 2.65 ps (-4.9 % pre-rad) pre-rad transmitter eye

12. GBTX ASIC Project (current stage) User Support – Creation and management of two CERN e-groups – GBTX-news to broadcast all important updates relative to the project – GBTX-support to serve as a feedback channel from users to developers – Provide technical support Production testing Part of the development of the new SAT board which will enable production testing – Automated testing of all working modes – Automated GBTX ASIC characterization – Expected ~1k GBTX to test early 2015 – End of full production expected in Q4 2015 (expected > 50k for production testing) p.leitao@cern.ch12http://cern.ch/proj-gbt

13. eCDR-PLL ASIC Project eCDR-PLL ASIC overview – Based on the eCDR IP block (F. Tavernier, 2013) using 130 nm techn. – Two operation modes: CDR (clock and data recovery circuit) PLL (clock multiplying PLL) – My work: Development of digital blocks: Control block, I2C slave, frequency divider, phase-shifter, lock monitoring, … p.leitao@cern.ch13http://cern.ch/proj-gbt

14. eCDR-PLL ASIC Project eCDR-PLL ASIC overview – Based on the eCDR IP block (F. Tavernier, 2013) using 130 nm techn. – Two operation modes: CDR (clock and data recovery circuit) PLL (clock multiplying PLL) – My work: Development of digital blocks: Control block, I2C slave, frequency divider, phase-shifter, lock monitoring, … p.leitao@cern.ch14http://cern.ch/proj-gbt ASIC presented at TWEPP’14 The eCDR-PLL IC, a Radiation-Tolerant ASIC for Clock and Data Recovery and Deterministic Phase Clock Synthesis In the Topical workshop on electronics for particle physics, Aix-en-Provence, FR, Sept (2014)

15. Further work Finish the eCDR-PLL ASIC – Prototype fabrication expected in Q1 2015 Continue with the GBTX project Finish the development of the production tests Test all GBTXs during the production stage Upcoming project: Low-power GBTX (LpGBTX) “Replica” of the GBTX but using 65 nm CMOS technology Low-power mode – 4.8 Gb/s bidirectional high-speed link – e-links @ 80, 160 and 320 Mb/s (uplink) High-speed mode – 9.6 Gb/s for the uplink, 4.8 Gb/s for the downlink – e-links @ 160, 320 and 640 Mb/s (uplink) p.leitao@cern.ch15http://cern.ch/proj-gbt

16. Further work Finish the eCDR-PLL ASIC – Prototype fabrication expected in Q1 2015 Continue with the GBTX project Finish the development of the production tests Test all GBTXs during the production stage Upcoming project: Low-power GBTX (LpGBTX) “Replica” of the GBTX but using 65 nm CMOS technology Low-power mode – 4.8 Gb/s bidirectional high-speed link – e-links @ 80, 160 and 320 Mb/s (uplink) High-speed mode – 9.6 Gb/s for the uplink, 4.8 Gb/s for the downlink – e-links @ 160, 320 and 640 Mb/s (uplink) p.leitao@cern.ch16http://cern.ch/proj-gbt Thank you for your time and attention!