A bit-streaming, pipelined multiuser detector for wireless communications Sridhar Rajagopal and Joseph R. Cavallaro Rice University This work is supported by Nokia, TI, TATP and NSF

2 Direct Reflections noise User 1 User 2 Base-station Jointly detect data of all users Multiuser detection Multiple access interference time amplitude

3 Benefits of multiuser detection Error rate vs. SNR SNR (in dB) Bit error rate Single-user (channel estimation + detection) Multi-user estimation+ Single-user detection Multi-user (channel estimation + detection)

4 Motivation Implement multiuser detection for 3G wireless CDMA base- station receivers Challenges: -large complexity -block based algorithms (latency) Unable to meet real-time requirements (3GPP) Kbps for 32 users with spreading = 32 chips/bit

5 Contributions Developed a simple architecture for asynchronous multiuser detection for CDMA [ +, x ] Bit-streaming - reduced latency - eliminates window edge computations - lower memory requirements Pipelined stages - higher throughput (with more hardware) Real-time implementation for multiuser detection now possible for 3GPP!

6 Asynchronous multiuser interference r i-1 riri r i+1 r i+2 Interference from previous bits of other users Interference from future bits of other users desired user I-1 Delay Interference due to past, current and future bits of other users I I I+1 I TIME Received Signal

7 Stage 2 Stage 3 PIC Stage 1 MF Received Signal r 1...r D Detected bits Channel Estimate B = A H A-diag(A H A) Channel Estimate A = [A 0 A 1 ]  I(D) Delay (D) Delay (D) Multistage Parallel Interference Cancellation (PIC) Conventional code matched filter

8 Block Pipelined Detector Variable latency [Worst case (1st bit)  D*latency per bit] 2 extra edge bit computations per stage. 11 MF 22 Bits TIME 1 MF 12 Bits PIC 1211 PIC 22 1 PIC 1211 PIC 22 1 PIC 1211 PIC 22

9 Bit-streaming the multiuser detection algorithm Savings in memory by D 2 Tri- diagonal Block Toeplitz matrix B [KD * KD] D- detection window length

10 Pipelining the multiuser detector Matched Filter (causal) PIC - Stage 1 PIC - Stage 2 PIC - Stage 3 TIME Latency = 2*latency per bit (D/2 speedup over block) eliminated edge bit computations.

11 Pipelined architecture for multiuser detection

12 FPGAs for pipelining DSPs not suitable for exploiting bit-level parallelism FPGAs - Flexibility of ASICs Good for parallelism and bit-level operations MF PIC (Stage 1) PIC (Stage 2) Received bits Detected bits DSP [x] FPGA1 [+] PIC (Stage 3) FPGA2 [+] FPGA3 [+]

13 Performance Comparisons t MF = O(K) t PIC = O(K 2 )

14 Prototype chip built at Rice Number of users supported: 4 Die size: 1.5mm x 1.5 mm at 0.5 micron Area used: ~85% Chip processing rate: 2Mbps/user

15 Summary Simple, bit-streaming pipelined multiuser detector Avoids block computations - Savings in memory by D 2 No edge bit computations in a window - 2/D computational savings per stage Lower constant latency by D/2 Leads to a Real-time implementation for 3GPP