2. DSPs in Wireless Communication Systems Vishwas Sundaramurthy {vishwas@rice.edu} Electrical and Computer Engineering Department, Rice University, Houston,TX.

3. Organization What are DSPs? –Comparison with other processors DSPs in Wireless communications Prototyping using DSPs –use of DSP boards Fixed point analysis We use DSPs for …

4. What are DSPs? u Digital Signal Processors u Optimized for signal processing u Work on a stream of data from the external world – “Real-Time” operation u Power efficient u Low cost

5. Why DSPs? u Digital signal processors Vs. Analog components – No variation in behavior with external factors – Easy duplication of specifications – Flexibility in setting parameters

6. DSPs Vs. general purpose processors u Harvard Architecture u Von Neumann Architecture Processor Core Memory Address Bus Data Bus Processor Core Memory - A Address Buses Data Buses Memory - B u MAC - Multiply Accumulate X + u Single cycle multiply u Faster clock speeds u Expensive

7. Use of MACs X +DDD++ XXX Eg. - FIR filter

8. DSPs Vs. GPPs u Data flow – Real time u Program “flow” Data InData Out DSP Section - A Function - B Section - C u Simpler Programming – High level languages u Flexibility to programmer – Coding in “C” – Optimization in assembly u Fixed point versions u Cool! u Hot!

9. Application Areas in Wireless Communication Systems u Digital cellular phones u Cellular base stations u Wireless data applications u Wireless local loops u Cordless phones u Pagers u GPS systems

10. A Cellular Handset TRANSMITTER RECEIVER Switch RF sectionA/D conv.Baseband section Detection Channel Decoding Channel Coding Spreading Modulation Source decoding Source Coding RF Amplification & De/Modulation A to D D to A DSP Demodulation Speaker Mic.

11. A Cellular Base-station SOURCE CODING CHANNEL CODING SPREADING TRANSMITTER K users Noise MULTIUSER RECEIVER DECODER DETECTOR DEMODULATION CHANNEL ESTIMATOR (RF) A/D SWITCHING DSPs MODULATION (RF)

12. System-on-a-chip Solutions Viterbi decoder demodulator and synchronization keypad interface protocol control de- interleaver speech decoder voice recognition DSP core  P core RAM & ROM Other logic A D down conversion Analog

13. C - CODE Algorithm Implemented using C - CODE MATLAB Compiler Algorithm Implemented as a MATLAB program C-code generator Algorithm implemented using a block diagram tool (SIMULINK) C - CODE DSP CODE GENERATION TOOLS C - Compiler Assembler Linker C - CODE ASM-CODEMACHINE LANGUAGE DSP EXECUTABLE DOWNLOADED TO DSP DSP DEBUGGER Watch registers and memory DSP Algorithm to be implemented Algorithm development: high-level evaluation to DSP implementation

14. Design flow for ASIC implementation COSSAP/SPW based analysis Fixed point analysis of blocks VHDL DSP function library VHDL description and simulation : Eg. Mentor Graphics' ModelSim VLSI design tools: area estimate : Eg. Synopsis' Design Compiler

15. Example: Adaptive Filtering Algorithms u Interference cancellation in the synchronous downlink by channel equalization x(i)x(i)x(i+F)x(i-F) A N-1 A N-2 A1A1 A1*A1* A N-2 * A N-1 * x(i+1 ) x(i- 1)  z(i)z(i)... Discretize Update Coefficients Compare Training Sequence r(t)r(t)... Chip- matched filter

16. Griffith's Chip Estimator Received downlink signal model: Griffith's chip estimator Correlator Channel impulse response r : received signal H : channel and pulse shaping filter response u : signal elements n : noise Estimate for u(i) (filter output): Adaptive filter coefficients with Filter coefficient (without preamble)

17. LMS-filter VHDL Model Filter Output: Filter coefficients update: W k : filter weight vector  : gain constant,  k  d k  y k  : the error, X k : the input sample vector d k : the desired response. Z x k Z Z... w 0k  k w Lk  k w 1k  k  + + y k...

18. Reference system u Downlink simulations in COSSAP Bit Source Channel Encoding InterleavingAdd Pilot Interfering users Base station transmitter (spreading and scrambling) 3-path Raleigh fading channel AWGN Chip- matched filter Griffith's chip estimator Channel estimate De- spreading De- interleaving Decoding Statistics

19. Fixed-point Analysis u COSSAP based simulation analysis u Fixed-point version of of the Adaptive filter only Cossap block diagram Floating- point to integer integer to Floating -point Griffith's Algorithm (integer)

20. Fixed-point Scaling ALU-1 MAC Coefficient Update ALU-2 Filter update X_i, X_q (^2 8 ) W_I, W_q (^2 14 ) Fil_i, Fil_q (^2 22 ) Downscale (v 2 28 ) W(+)_i, W(+)_q (^2 42 ) Downscale (v 2 6 ) (^2 16 ) X Step-Size (^ 2 18 ) (^2 24 )

21. Fixed-point Scaling Observed signal range: u chip matched filter output : –50 to +50 u channel coefficients: -0.5 to 0.5 16 bits 9 bits 17 bits

22. Signal widths

23. TI TMS320C6201 Development System u VLIW Architecture u 1600 MIPS Peak u 256 KB SRAM u 8 MB DRAM u PCI Interface

24. TI TMS320C6X architecture

25. Wideband W-CDMA Simulation Testbed u Develop an integrated software testbed u Unified framework to evaluate new algorithms for coding, synchronization, detection, etc. u Hardware/Software Co-Design Simulink, Matlab, “C” u Simulation Acceleration What we do with DSPs...

26. CDMA Wireless Link SOURCE CODING CHANNEL CODING SPREADINGMODULATION TRANSMITTER RECEIVER Detected bits of K users User’s data bits K users DECODER DETECTOR DEMODULATION CHANNEL ESTIMATOR Noise

27. Wireless Channel User_Data Show Stats Update Parameters Decorrelating Detector Multiuser Detector Error Counter Chip MF Max. Likelihood Channel Est. Channel Estimation CDMA Wireless System Testbed Simulink Version Parameters Multiuser Detection Channel Estimation AWGN Channel User Data Error Rate Calculation Statistics Chip matched filter

28. Prototyping Methodology Display and Analysis of Data Simulink C - CodeMatlab Code Block Diagram Libraries Algorithms With RTW support for DSP hardware Workstation DSP hardware DSP Code Generation Tools RTW generated C - Code

29. Current Infrastructure u 400MHz Pentium PC host u Two TI TMS320C6201 DSP Development Boards (EVMs) u Optimizing “C” compiler and code generation tools u MS Visual Studio development environment

30. Future Environment PCI TIM (TI C40 Module) carrier C62/C67 DSP TIMs Xilinx Virtex FPGA module

31. Summary u What are DSPs? + Special features u Issues in algorithm development on DSP boards – Prototyping – Fixed Point Analysis u DSPs in Wireless communications – DSPs in the wireless testbed project