Main Memory -Victor Frandsen

Overview Types of Memory The CPU & Main Memory Types of RAM Properties of DRAM Types of DRAM & Enhanced DRAM Error Detection & Correction

Types of Memory Registers Cache Main Memory Secondary Storage (Disks) Off-line Storage (Tape)

Types of Memory Registers Cache Main Memory Secondary Storage (Disks) Off-line Storage (Tape) } Random Access Memory

“Random” – all information can be accessed in the same amount of time. Types of RAM Static RAM (SRAM) Dynamic RAM (DRAM)

Properties of DRAM A DRAM cell stores each bit on a capacitor. DRAM are susceptible to premature discharging.

The CPU & Main Memory The CPU communicates with Main Memory through the Memory Controller located in the North Bridge of the Chipset.

Types of DRAM DRAM is commercially available variety of standards. Two of the most common are: Dual in-line Memory Module (DIMM)  Memory chips & electrical contacts on both sides. Single in-line Memory Module (SIMM)  Memory chips & electrical contacts on only one side.

DRAM A single memory module consists of many DRAM chips. Each DRAM chip consists of supercells organized in a Rectangular Array. Each supercell contains a certain number of individual DRAM cells or bits. A chip of 16 supercells, each with 8 bits, is a 16 x 8 DRAM chip. That chip holds 128 bits.

DRAM To access a supercell a signal is sent from the Memory Controller specifying a row. That row is loaded into an Internal Row Buffer. A subsequent signal is sent specifying a column. The information of that supercell is sent to the Memory Controller.

DRAM A SIMM or DIMM with 8 2^23 x 8 DRAM chips is a 64MB module. To access a 64-bit doubleword, the controller converts a memory address into a supercell coordinates (i,j). That coordinates is sent to the 8 DRAM chips and each corresponding supercell of row i and col j is returned to the controller which forms the 64-bit doubleword.

Enhanced DRAM Fast Page Mode DRAM & Extended Data Out DRAM (FPM DRAM & EDO DRAM) Synchronous DRAM (SDRAM) Double Data Rate SDRAM (DDR DRAM) DDR2 SDRAM Rambus DRAM (RDRAM)

Error Detection Parity bits are used for error detection. RAM with parity bits have an extra bit per byte. RAM can use either Odd Parity or Even Parity. An Even Parity chip turns the parity bit to 0 when the sum of all the 1’s in the byte are even.

Error Correction Codes Parity bits can not correct an error. Error correction codes such as a Hamming Code can detect and correct single bit errors.

Sources Computer Architecture and Organization: An Integrated Approach Miles Murdocca & Vincent Heuring Computer Systems: A Programmers Perspective Randal E. Bryant & David R. O’Hallaron Howstuffworks.com/ram.htm