N A S A G O D D A R D S P A C E F L I G H T C E N T E R I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y Earth Atmosphere Solar-Occultation Imager (EASI) Electrical Design Estimates C. Paul Earle 2 August 2002

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep22 August 2002EASI Timing (1pps) Main Electronics (warm) RISC Processor (RAD6000) & Memory 1553 I/F +28V Supply S/C C&DH Functional Block Diagram Figure V Survival Power DC/DC Converter Telescope Mechanism Control Box H/K 5 Si Arrays (128x128) USES Data Compression Cryo-Cooler Science Data I/F Storage/ Downlink Readout Electronics +28V Supply Actuators Thermal Control 2 InSb Arrays (1Kx1K) Readout Electronics Science Centroiding Fringe Sensing Si Array (128x128) Readout Electronics

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep32 August 2002EASI Two (2) InSb (1K x 1K) Array For Science - 10mSec Integration, 90mSec Readout, 18 bits/pix - Full Frame Readout Mode (Diagnostic) - Science Readout Mode (~10% Focal Plane) Five (5) Si (128 x 128) Array for Centroiding One (1) Si (128 x 128) Array for Fringe Sensing Design Assumptions

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep42 August 2002EASI Assumptions: 10mSec Integration, 90mSec Readout, and 18bits/pix  FPA Readout Rate ~ 2(1Mpix)x(18 bits/pix)/(90mSec) ~ 400Mbps (avg) Current Downlink (D/L) Capability from L-2: ~ 20Mbps  1 Frame every 1.8 Sec (ie. 36Mpix/20Mbps) - (meets science requirements) Full-Frame Mode (Diagnostic): - Readout 1 Frame every 1.8 Sec (vs. 10 Frames/Sec), - Onboard Data Compression (at least 2:1), Consider Utilizing GSFC’s Programmable Compression Chip (USES) - Consider adding Memory Board and limit Readout (say n Seconds) Science Mode (Onboard Processing): - Readout 10 % (or less) of Focal Plane < 40Mbps - Compute Average of 10 Frames < 4Mbps (meets D/L constraints) Science Data Rate

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep52 August 2002EASI Main Electronics Box 1 Processor & H/K Board 2 Main FPE Control Boards 2 Main FPE Analog Boards 1 CCD Readout Board (Centroiding & Fringe Sensing) 1 Thermal Control Board 1 Power Board Circuit Board Functional Allocation

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep62 August 2002EASI Figure 2. Main Electronics Box Summary 1 Processor& H/K (4W) 2 FPE Control 3W) 12 in Estimated Mass ~ 7 Kg Estimated Power ~ 66 Watts (Avg.) Estimated Size ~ (9 x 10 x 15) in. Main Electronics Box 2 Power 20W) 8 in 1 Thermal Control (4W) 2 FPE Analog 4W) 1 CCD Readout (4W) 15 in 10 in 9 in

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep72 August 2002EASI Power Requirement Summary End ItemsAvg. Power 1 Main Electronic Box~ 66 Watts 1 Mechanisms & Control Box~ 66 Watts Heaters~ 100 Watts 1 Cryo-Cooler~ 100 Watts * 1 Star Tracker 10 Watts Instrument Total:~ 312 Watts Spacecraft Power Bus Requirement * 70 Watts + 30 Watts for conditioning

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep82 August 2002EASI No Electrical Design Issues or Concerns at the Instrument level. Potential Power Subsystem Challenges Exist For Solar Array Sizing At The Observatory Level Due To Solar Occultation In L2 Orbit. Focal Plane Readout Electronics Estimates Extrapolated From As-Built IRAC Design. Development cost ~ $4M- $5M (IRAC actuals). Includes Design, Fabrication, & Test of one Flight Unit and one Engineering Unit. Conclusion

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep92 August 2002EASI Backup Slides (Electrical Design Estimates)

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep102 August 2002EASI Processor & H/K Board CPU RAD 6000 Startup ROM EEPROM Memory (Data Processing) Ethernet I/F 1553 I/F RAM (Data Processing) Time Stamp Function S/C 1pps S/W Dev. Figure 3. Compression Chip (USES) Housekeeping MUX & A/D RAM - UTMC (1Gbits Stack)

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep112 August 2002EASI FPE Analog Board Figure 4. (1 of 2 boards shown) A/D Latches FPE Data DSP I/F Detector Output Pre-Amp convert latch A/D Latches FPE Data DSP I/F Detector Output Pre-Amp convert latch A/D Latches FPE Data DSP I/F Detector Output Pre-Amp convert latch A/D Latches FPE Data DSP I/F Detector Output Pre-Amp convert latch 18

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep122 August 2002EASI FPE Control Board Figure 5. (1 of 2 boards shown) State Machine (ACTEL) Level Shifters Array Clocks Array Row, Col DC Biases Analog MUX Array Biases Analog Monitor Data convert latch Address Processor I/F

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep132 August 2002EASI Thermal Control Board Figure 6. DAC HK Mux V Ref I Source I+I+ I+I+ V+V+ Heater Current Heater Voltage T sensor Voltage T sensor Current + - From Processor To Central HK Heater T sensor From Processor (1 of n circuits shown)

Electrical Design Estimates I n s t r u m e n t S y n t h e s i s a n d A n a l y s i s L a b o r a t o r y C. Paul Earlep142 August 2002EASI Main Electronics Power Board DC/DC Converter (70% eff.) +28 VDC - + Current Sense - + Voltage Sense +15 V I+I+ +5 V I+I+ Figure 7.