1 Appendix J Authors: John Hennessy & David Patterson.

Slides:

Advertisements

Similar presentations

EET 1131 Unit 7 Arithmetic Operations and Circuits

Advertisements

THE ARITHMETIC-LOGIC UNIT. BINARY HALF-ADDER BINARY HALF-ADDER condt Half adder InputOutput XYSC

Basic Integer Arithmetic Building Block

Tutorial: Wednesday Week 3 Hand in on Monday, Do the questions for tutorials 1 & 2 at the back of the course notes (answers to tutorial 3 will be published.

Arithmetic Operations and Circuits

UNIVERSITY OF MASSACHUSETTS Dept

EE 382 Processor DesignWinter 98/99Michael Flynn 1 AT Arithmetic Most concern has gone into creating fast implementation of (especially) FP Arith. Under.

Copyright 2008 Koren ECE666/Koren Part.6b.1 Israel Koren Spring 2008 UNIVERSITY OF MASSACHUSETTS Dept. of Electrical & Computer Engineering Digital Computer.

Chapter 3 Arithmetic for Computers. Chapter 3 — Arithmetic for Computers — 2 FIGURE 3.1 Binary addition, showing carries from right to left. The rightmost.

Lecture 9 Sept 28 Chapter 3 Arithmetic for Computers.

Chapter 6 Arithmetic. Addition Carry in Carry out

UNIVERSITY OF MASSACHUSETTS Dept

Introduction to VLSI Circuits and Systems, NCUT 2007 Chapter 12 Arithmetic Circuits in CMOS VLSI Introduction to VLSI Circuits and Systems 積體電路概論賴秉樑 Dept.

Modern VLSI Design 2e: Chapter 6 Copyright  1998 Prentice Hall PTR Topics n Shifters. n Adders and ALUs.

Slide 4-1 Copyright © 2005 Pearson Education, Inc. SEVENTH EDITION and EXPANDED SEVENTH EDITION.

COE 308: Computer Architecture (T041) Dr. Marwan Abu-Amara Integer & Floating-Point Arithmetic (Appendix A, Computer Architecture: A Quantitative Approach,

CSE 246: Computer Arithmetic Algorithms and Hardware Design Instructor: Prof. Chung-Kuan Cheng Winter 2004 Lecture 7.

Computer Arithmetic Integers: signed / unsigned (can overflow) Fixed point (can overflow) Floating point (can overflow, underflow) (Boolean / Character)

Arithmetic Operations and Circuits

Number Systems Lecture 02.

Chapter 3 Digital Logic Structures. Copyright © The McGraw-Hill Companies, Inc. Permission required for reproduction or display. 3-2 Building Functions.

3-1 Chapter 3 - Arithmetic Computer Architecture and Organization by M. Murdocca and V. Heuring © 2007 M. Murdocca and V. Heuring Computer Architecture.

Chapter 6-2 Multiplier Multiplier Next Lecture Divider

Binary Arithmetic Stephen Boyd March 14, Two's Complement Most significant bit represents sign. 0 = positive 1 = negative Positive numbers behave.

3-1 Chapter 3 - Arithmetic Principles of Computer Architecture by M. Murdocca and V. Heuring © 1999 M. Murdocca and V. Heuring Principles of Computer Architecture.

Basic Arithmetic (adding and subtracting)

Copyright 1995 by Coherence LTD., all rights reserved (Revised: Oct 97 by Rafi Lohev, Oct 99 by Yair Wiseman, Sep 04 Oren Kapah) IBM י ב מ 10-1 The ALU.

Chapter 4 – Arithmetic Functions and HDLs Logic and Computer Design Fundamentals.

Introduction to Computer Organization and Architecture Lecture 10 By Juthawut Chantharamalee wut_cha/home.htm.

Lec 13Systems Architecture1 Systems Architecture Lecture 13: Integer Multiplication and Division Jeremy R. Johnson Anatole D. Ruslanov William M. Mongan.

CSE 241 Computer Organization Lecture # 9 Ch. 4 Computer Arithmetic Dr. Tamer Samy Gaafar Dept. of Computer & Systems Engineering.

Basic Arithmetic (adding and subtracting)

Multiplication of signed-operands

Digital Kommunikationselektronik TNE027 Lecture 2 1 FA x n –1 c n c n1- y n1– s n1– FA x 1 c 2 y 1 s 1 c 1 x 0 y 0 s 0 c 0 MSB positionLSB position Ripple-Carry.

1 Chapter 7 Computer Arithmetic Smruti Ranjan Sarangi Computer Organisation and Architecture PowerPoint Slides PROPRIETARY MATERIAL. © 2014 The McGraw-Hill.

55:035 Computer Architecture and Organization Lecture 5.

Advanced VLSI Design Unit 05: Datapath Units. Slide 2 Outline  Adders  Comparators  Shifters  Multi-input Adders  Multipliers.

1 CS103 Guest Lecture Number Systems & Conversion Bitwise Logic Operations.

Computer Arithmetic and the Arithmetic Unit Lesson 2 - Ioan Despi.

1 Copyright © 2013 Elsevier Inc. All rights reserved. Chapter 5 Digital Building Blocks.

Division Harder Than Multiplication Because Quotient Digit Selection/Estimation Can Have Overflow Condition – Divide by Small Number OR even Worse – Divide.

1 Arithmetic I Instructor: Mozafar Bag-Mohammadi Ilam University.

Topics covered: Arithmetic CSE243: Introduction to Computer Architecture and Hardware/Software Interface.

COE 308: Computer Architecture (T032) Dr. Marwan Abu-Amara Integer & Floating-Point Arithmetic (Appendix A, Computer Architecture: A Quantitative Approach,

CS/EE 3700 : Fundamentals of Digital System Design Chris J. Myers Lecture 5: Arithmetic Circuits Chapter 5 (minus 5.3.4)

C-H1 Lecture Adders Half adder. C-H2 Full Adder si is the modulo- 2 sum of ci, xi, yi.

Computer Architecture Lecture Notes Spring 2005 Dr. Michael P. Frank Competency Area 4: Computer Arithmetic.

CPEN Digital System Design

Addition, Subtraction, Logic Operations and ALU Design

ECE/CS 552: Arithmetic I Instructor:Mikko H Lipasti Fall 2010 University of Wisconsin-Madison Lecture notes partially based on set created by Mark Hill.

ECE DIGITAL LOGIC LECTURE 15: COMBINATIONAL CIRCUITS Assistant Prof. Fareena Saqib Florida Institute of Technology Fall 2015, 10/20/2015.

Chapter 8 Computer Arithmetic. 8.1 Unsigned Notation Non-negative notation  It treats every number as either zero or a positive value  Range: 0 to 2.

UNIT 2. ADDITION & SUBTRACTION OF SIGNED NUMBERS.

Arithmetic Circuits I. 2 Iterative Combinational Circuits Like a hierachy, except functional blocks per bit.

1. Copyright  2005 by Oxford University Press, Inc. Computer Architecture Parhami2 Figure 11.1 Multiplication of 4-bit numbers in dot notation.

Instructor: Alexander Stoytchev CprE 281: Digital Logic.

Chapter 3 Arithmetic for Computers

Part II : Lecture III By Wannarat.

UNIVERSITY OF MASSACHUSETTS Dept

Multipliers Multipliers play an important role in today’s digital signal processing and various other applications. The common multiplication method is.

Invitation to Computer Science, Java Version, Third Edition

Registers and Counters Register : A Group of Flip-Flops. N-Bit Register has N flip-flops. Each flip-flop stores 1-Bit Information. So N-Bit Register Stores.

Appendix D Mapping Control to Hardware

King Fahd University of Petroleum and Minerals

Computer Architecture

Reading: Study Chapter (including Booth coding)

Montek Singh Mon, Mar 28, 2011 Lecture 11

Appendix J Authors: John Hennessy & David Patterson.

Presentation transcript:

1 Appendix J Authors: John Hennessy & David Patterson

2 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.1 Ripple-carry adder, consisting of n full adders. The carry-out of one full adder is connected to the carry-in of the adder for the next most-significant bit. The carries ripple from the least-significant bit (on the right) to the most-significant bit (on the left).

3 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.2 Block diagram of (a) multiplier and (b) divider for n-bit unsigned integers. Each multiplication step consists of adding the contents of P to either B or 0 (depending on the low-order bit of A), replacing P with the sum, and then shifting both P and A one bit right. Each division step involves first shifting P and A one bit left, subtracting B from P, and, if the difference is nonnegative, putting it into P. If the difference is nonnegative, the low-order bit of A is set to 1.

4 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.3 Numerical example of (a) restoring division and (b) nonrestoring division.

5 Copyright © 2011, Elsevier Inc. All rights Reserved.

6 Figure J.9 Examples of rounding a multiplication. Using base 10 and p = 3, parts (a) and (b) illustrate that the result of a multiplication can have either 2p – 1 or 2p digits; hence, the position where a 1 is added when rounding up (just left of the arrow) can vary. Part (c) shows that rounding up can cause a carry-out.

7 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.10 The two cases of the floating-point multiply algorithm. The top line shows the contents of the P and A registers after multiplying the significands, with p = 6. In case (1), the leading bit is 0, and so the P register must be shifted. In case (2), the leading bit is 1, no shift is required, but both the exponent and the round and sticky bits must be adjusted. The sticky bit is the logical or of the bits marked s.

8 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.13 Newton’s iteration for zero finding. If x i is an estimate for a zero of f, then x i +1 is a better estimate. To compute x i +1, find the intersection of the x-axis with the tangent line to f at f(x i ).

9 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.14 Pure carry-lookahead circuit for computing the carry-out cn of an n-bit adder.

10 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.15 First part of carry-lookahead tree. As signals flow from the top to the bottom, various values of P and G are computed.

11 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.16 Second part of carry-lookahead tree. Signals flow from the bottom to the top, combining with P and G to form the carries.

12 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.17 Complete carry-lookahead tree adder. This is the combination of Figures J.15 and J.16. The numbers to be added enter at the top, flow to the bottom to combine with c0, and then flow back up to compute the sum bits.

13 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.18 Carry-skip adder. This is a 20-bit carry-skip adder (n = 20) with each block 4-bits wide (k = 4).

14 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.19 Combination of CLA and ripple-carry adder. In the top row, carries ripple within each group of four boxes.

15 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.20 Simple carry-select adder. At the same time that the sum of the low-order 4 bits is being computed, the high-order bits are being computed twice in parallel: once assuming that c 4 = 0 and once assuming c 4 = 1.

16 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.21 Carry-select adder. As soon as the carry-out of the rightmost block is known, it is used to select the other sum bits.

17 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.23 SRT division of / The quotient bits are shown in bold, using the notation for –1.

18 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.24 Carry-save multiplier. Each circle represents a (3,2) adder working independently. At each step, the only bit of P that needs to be shifted is the low-order sum bit.

19 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.26 Multiplication of –7 times –5 using radix-4 Booth recoding. The column labeled L contains the last bit shifted out the right end of A.

20 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.27 An array multiplier. The 5-bit number in A is multiplied by b 4 b 3 b 2 b 1 b 0. Part (a) shows the block diagram, (b) shows the inputs to the array, and (c) expands the array to show all the adders.

21 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.28 Multipass array multiplier. Multiplies two 8-bit numbers with about half the hardware that would be used in a one-pass design like that of Figure J.27. At the end of the second pass, the bits flow into the CPA. The inputs used in the first pass are marked in bold.

22 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.29 Even/odd array. The first two adders work in parallel. Their results are fed into the third and fourth adders, which also work in parallel, and so on.

23 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.30 Wallace tree multiplier. An example of a multiply tree that computes a product in 0(log n) steps.

24 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.31 Signed-digit addition table. The leftmost sum shows that when computing 1 + 1, the sum bit is 0 and the carry bit is 1.

25 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.32 Quotient selection for radix-2 division. The x-axis represents the Ith remainder, which is the quantity in the (P,A) register pair. The y-axis shows the value of the remainder after one additional divide step. Each bar on the right-hand graph gives the range of r i values for which it is permissible to select the associated value of q i.

26 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.33 Quotient selection for radix-4 division with quotient digits –2, –1, 0, 1, 2.

27 Copyright © 2011, Elsevier Inc. All rights Reserved. Figure J.35 Example of radix-4 SRT division. Division of 149 by 5.

28 Copyright © 2011, Elsevier Inc. All rights Reserved. A Figure J.37A Chip layout for the TI 8847, MIPS R3010, and Weitek In the left-hand columns are the photomicrographs; the right-hand columns show the corresponding floor plans.

29 Copyright © 2011, Elsevier Inc. All rights Reserved. B Figure J.37B Chip layout for the TI 8847, MIPS R3010, and Weitek In the left-hand columns are the photomicrographs; the right-hand columns show the corresponding floor plans.