CSE 370 – Winter Hardware Description Languages - 1 Overview zLast lecture yRipple and Carry-Lookahead Adders zToday yALU yAn Introduction to Hardware Description Languages (HDL)

CSE 370 – Winter Hardware Description Languages - 2 A0 B0 Cin A1 B1 A2 B2 A3 B3 A0 B0 Cin A1 B1 A2 B2 A3 B3 Carry-lookahead implementation (cont’d) zCarry-lookahead logic generates individual carries ysums computed much more quickly in parallel yhowever, cost of carry logic increases with more stages

CSE 370 – Winter Hardware Description Languages - 3 A0 B0 Cin A1 B1 A2 B2 A3 B3 G0 + P0 C0 G1 + P1 G0 + P1 P0 C0 G2 + P2 G1 + P2 P1 G0 + P2 P1 P0 C0 GP0= P3 P2 P1 P0 GG0= G3 + P3 G2 + P3 P2 G1 + P3 P2 P1 G0+ P3 P2 P1 P0 C0 Gi = Ai Bi Pi = Ai xor Bi Gi, Pi, available at time 1 GiPi available at time 2 GiPi + GjPj available at time 3 GP0 available at time 2 GG0 available at time 3

CSE 370 – Winter Hardware Description Languages - 4 Lookahead Carry Unit C0 P0G0P1G1P2G2P3G3 C3 C2C1 C0 @2 C16 A[15-12]B[15-12] C12 S[15-12] A[11-8]B[11-8] C8 S[11-8] A[7-4]B[7-4] A[3-0]B[3-0] PG 4-bit Adder PG PG PG Carry-lookahead adder with cascaded carry-lookahead logic zCarry-lookahead adder y4 four-bit adders with internal carry lookahead ysecond level carry lookahead unit extends lookahead to 16 bits

CSE 370 – Winter Hardware Description Languages Bit Adder [3:0] C0 C4 4-bit adder [7:4] 1 C8 0 five 2:1 mux adder low adder high 01 4-bit adder [7:4] C8S7 S6 S5S4S3S2 S1 S0 Carry-select adder zRedundant hardware to make carry calculation go faster ycompute two high-order sums in parallel while waiting for carry-in yone assuming carry-in is 0 and another assuming carry-in is 1 yselect correct result once carry-in is finally computed

CSE 370 – Winter Hardware Description Languages - 6 Arithmetic Logic Unit zInputs: n-bit words yA = A n-1 A n-2 … A 0 ; B = B n-1 B n-2 … B 0 ; Carry-in C 0 zOutput: n+1-bit word + some signals (overflow, zero, etc.) yF = F n F n-1 …F 0 where F n is in fact carry-out zControl inputs. For example: yM = 0 “logic” (i.e., bit wise) operations yM = 1 “arithmetic” (with carry) operations yOther control bits S m,S m-1,…,S 0 for selecting particular “opcodes”

CSE 370 – Winter Hardware Description Languages - 7 logical and arithmetic operations not all operations appear useful, but "fall out" of internal logic S S Function Fi = Ai Fi = not Ai Fi = Ai xor Bi Fi = Ai xnor Bi Comment input Ai transferred to output complement of Ai transferred to output compute XOR of Ai, Bi compute XNOR of Ai, Bi M = 0, logical bitwise operations M = 1, C0 = 0, arithmetic operations F = A F = not A F = A plus B F = (not A) plus B input A passed to output complement of A passed to output sum of A and B sum of B and complement of A M = 1, C0 = 1, arithmetic operations F = A plus 1 F = (not A) plus 1 F = A plus B plus 1 F = (not A) plus B plus 1 increment A twos complement of A increment sum of A and B B minus A ALU specification (1-bit slice)

CSE 370 – Winter Hardware Description Languages - 8 M011M011 S S Ci X X X X X X X X X X X X Ai Bi X X X X X X X X X X X X Fi Ci+1 X X X X X X X X X X X X X X X X Arithmetic logic unit design (cont’d) zSample ALU – truth table

CSE 370 – Winter Hardware Description Languages gates Arithmetic logic unit design (cont’d) zSample ALU – multi-level discrete gate logic implementation (via a CAD tool)

CSE 370 – Winter Hardware Description Languages - 10 first-level gates use S0 to complement Ai S0 = 0causes gate X1 to pass Ai S0 = 1causes gate X1 to pass Ai' use S1 to block Bi S1 = 0causes gate A1 to make Bi go forward as 0 (don't want Bi for operations with just A) S1 = 1causes gate A1 to pass Bi use M to block Ci M = 0causes gate A2 to make Ci go forward as 0 (don't want Ci for logical operations) M = 1causes gate A2 to pass Ci other gates for M=0 (logical operations, Ci is ignored) Fi = S1 Bi xor (S0 xor Ai) = S1'S0' ( Ai ) + S1'S0 ( Ai' ) + S1 S0' ( Ai Bi' + Ai' Bi ) + S1 S0 ( Ai' Bi' + Ai Bi ) for M=1 (arithmetic operations) Fi = S1 Bi xor ( ( S0 xor Ai ) xor Ci ) = Ci+1 = Ci (S0 xor Ai) + S1 Bi ( (S0 xor Ai) xor Ci ) = just a full adder with inputs S0 xor Ai, S1 Bi, and Ci Arithmetic logic unit design (cont’d) zSample ALU – clever multi-level implementation (see Katz for details)

CSE 370 – Winter Hardware Description Languages - 11 Summary for examples of combinational logic zCombinational logic design process yformalize problem: encodings, truth-table, equations ychoose implementation technology (ROM, PAL, PLA, discrete gates) yimplement by following the design procedure for that technology zBinary number representation ypositive numbers the same ydifference is in how negative numbers are represented y2s complement easiest to handle: one representation for zero, slightly complicated complementation, simple addition zCircuits for binary addition ybasic half-adder and full-adder ycarry lookahead logic ycarry-select zALU Design yspecification, implementation

CSE 370 – Winter Hardware Description Languages - 12 Hardware description languages (HDL) zDescribe hardware at varying levels of abstraction (HDLs are HLLs) ychip densities increase hence design complexity increases zStructural description ytextual replacement for schematic (because of increase in complexity) yhierarchical composition of modules from primitives zBehavioral/functional description ydescribe what module does, not how ysynthesis generates circuit for module zSimulation semantics

CSE 370 – Winter Hardware Description Languages - 13 HDLs zAbel (circa 1983) - developed by Data-I/O ytargeted to programmable logic devices (PLAs, PALs etc.) ynot good for much more than state machines zISP (circa 1977) - research project at CMU ysimulation, but no synthesis zVerilog (circa 1985) - developed by Gateway (now part of Cadence) ysimilar to Pascal and C ydelays is only interaction with simulator yfairly efficient and easy to write yIEEE standard zVHDL (circa 1987) - DoD sponsored standard y“V” is for “VHSIC” (very high speed integrated circuit) ysimilar to Ada (emphasis on re-use and maintainability) ysimulation semantics visible yvery general but verbose yIEEE standard

CSE 370 – Winter Hardware Description Languages - 14 Verilog zSupports structural and behavioral descriptions zStructural yexplicit structure of the circuit ye.g., each logic gate instantiated and connected to others zBehavioral yprogram describes input/output behavior of circuit ymany structural implementations could have same behavior ye.g., different implementation of one Boolean function zWe’ll only be using behavioral Verilog yrely on schematic for structural constructs

CSE 370 – Winter Hardware Description Languages - 15 Verilog capabilities (overview) zHierarchical design using instantation of modules zA module, like a procedure in a C-like language, has a name, input/output ports, and a body zA module is not called like a procedure. It is instantiated. yInputs are monitored. Upon change, the output is changed. yCan be done continuously, or under some conditions yOutput can be instantaneous, or after some delay yThe module stays around for the lifetime of the program

CSE 370 – Winter Hardware Description Languages - 16 module xor_gate (out, a, b); input a, b; output out; wire abar, bbar, t1, t2; inverter invA (abar, a); inverter invB (bbar, b); and_gate and1 (t1, a, bbar); and_gate and2 (t2, b, abar); or_gate or1 (out, t1, t2); endmodule Structural model

CSE 370 – Winter Hardware Description Languages - 17 module and_gate (out, in1, in2); input in1, in2; output out; reg out; assign #2 out = in1 & in2; endmodule Simple behavioral model zContinuous assignment; Input continuously monitored; Can be used for combinational circuits delay from input change to output change Required key wordNamePort list

CSE 370 – Winter Hardware Description Languages - 18 module and_gate (out, in1, in2); input in1, in2; output out; reg out; or in2) begin #2 out = in1 & in2; end endmodule Simple behavioral model zalways block; “infinite-loop”-like assignment; output changes every time input changes simulation register - keeps track of value of signal specifies when block is executed ie. triggered by which signals

CSE 370 – Winter Hardware Description Languages - 19 Module Hierarchy (Basic idea) zConnect modules together to form larger modules zExample: yBuild an AND gate by 2 NAND gates in series module NAND2 (in1, in2, out); input in1, in2; output out; assign out = ~(in1 & in2); endmodule module AND2(in1,in2,out); input in1,in2; output out; wire w1; // to connect the 2 NAND's NAND2 nand1(in1,in2,w1); NAND2 nand2(w1,w1,out); endmodule

CSE 370 – Winter Hardware Description Languages - 20 module stimulus (a, b); output a, b; reg [1:0] cnt; initial begin cnt = 0; repeat (4) begin #10 cnt = cnt + 1; $display time=%d, a=%b, b=%b, cnt=%b", $time, a, b, cnt); end #10 $finish; end assign a = cnt[1]; assign b = cnt[0]; endmodule Driving a simulation 2-bit vector initial block executed only once at start of simulation (in contrast with “always”) directive to stop simulation print to a console

CSE 370 – Winter Hardware Description Languages - 21 Complete Simulation zInstantiate stimulus component and device to test in a schematic

CSE 370 – Winter Hardware Description Languages - 22 module Compare1 (A, B, Equal, Alarger, Blarger); input A, B; output Equal, Alarger, Blarger; assign #5 Equal = (A & B) | (~A & ~B); assign #3 Alarger = (A & ~B); assign #3 Blarger = (~A & B); endmodule Comparator Example

CSE 370 – Winter Hardware Description Languages - 23 module life (n0, n1, n2, n3, n4, n5, n6, n7, self, out); input n0, n1, n2, n3, n4, n5, n6, n7, self; output out; reg out; reg [7:0] neighbors; reg [3:0] count; reg [3:0] i; assign neighbors = {n7, n6, n5, n4, n3, n2, n1, n0}; or self) begin count = 0; for (i = 0; i < 8; i = i+1) count = count + neighbors[i]; out = (count == 3); out = out | ((self == 1) & (count == 2)); end endmodule More Complex Behavioral Model

CSE 370 – Winter Hardware Description Languages - 24 Hardware Description Languages vs. Programming Languages zProgram structure yinstantiation of multiple components of the same type yspecify interconnections between modules via schematic yhierarchy of modules (only leaves can be HDL in DesignWorks) zAssignment ycontinuous assignment (logic always computes) ypropagation delay (computation takes time) ytiming of signals is important (when does computation have its effect) zData structures ysize explicitly spelled out - no dynamic structures yno pointers zParallelism yhardware is naturally parallel (must support multiple threads) yassignments can occur in parallel (not just sequentially)

CSE 370 – Winter Hardware Description Languages - 25 Hardware Description Languages and Combinational Logic zModules - specification of inputs, outputs, bidirectional, and internal signals zContinuous assignment - a gate's output is a function of its inputs at all times (doesn't need to wait to be "called") zPropagation delay- concept of time and delay in input affecting gate output zComposition - connecting modules together with wires zHierarchy - modules encapsulate functional blocks zSpecification of don't care conditions