Three-state devices Multiplexers

Slides:

Advertisements

Similar presentations

Computer Organization, Bus Structure

Advertisements

Part 4: combinational devices

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.

Encoders Three-state devices Multiplexers

EE 261 – Introduction to Logic Circuits

Digital Logic Design Week 7 Encoders, Decoders, Multiplexers, Demuxes.

Combinational Circuits

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR, Parity Circuits, Comparators.

Decoders/DeMUXs CS370 – Spring Decoder: single data input, n control inputs, 2 outputs control inputs (called select S) represent Binary index of.

Speical purpose Encoders/Comparators

Code Converters, Multiplexers and Demultiplexers

CS 151 Digital Systems Design Lecture 15 Magnitude Comparators and Multiplexers.

CSCE 211: Digital Logic Design Chin-Tser Huang University of South Carolina.

Multiplexers, Decoders, and Programmable Logic Devices

1 EE365 Three-state Outputs Encoders Multiplexers XOR gates.

Combinational Logic Building Blocks

Combinational Logic and Verilog

ECE 301 – Digital Electronics Multiplexers and Demultiplexers (Lecture #12)

Multiplexer MUX. 2 Multiplexer Multiplexer (Selector)  2 n data inputs,  n control inputs,  1 output  Used to connect 2 n points to a single point.

EE365 Adv. Digital Circuit Design Clarkson University Lecture #8 Buffers, Drivers, Encoders, MUXs & XORs.

طراحی مدارهای منطقی نیمسال دوم دانشگاه آزاد اسلامی واحد پرند.

 Combinational circuit that selects binary information from one of many input lines and directs information to a single output line.

Multiplexers DeMultiplexers XOR gates

Adders, subtractors, ALUs

Shannon’s Expansion Muxes and Encoders. Tri-State Buffers  A tri-state buffer has one input x, one output f and one control line e Z means high impedance,

Combinational Logic Chapter 4.

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexers.

Decoders and Multiplexers Prof. Sin-Min Lee Department of Computer Science San Jose State University.

Encoders Three-state Outputs Multiplexers XOR gates.

DIGITAL SYSTEMS Logic design practice Rudolf Tracht and A.J. Han Vinck.

Documentation Standards Circuit specification. –Description of what the system is supposed to do, including a description of all inputs and outputs and.

ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Adders, subtractors, ALUs.

Fall 2004EE 3563 Digital Systems Design EE3563 Multiplexers  A multiplexer is a digital switch  Allows a device to select a single line from many  Some.

9/15/09 - L15 Decoders, Multiplexers Copyright Joanne DeGroat, ECE, OSU1 Decoders and Multiplexer Circuits.

Combinational Design, Part 3: Functional Blocks

Multiplexers XOR gates. Multiplexers A multiplexer is a digital switch - it connects data from one of n sources to its output. An n-input and b-bit multiplexer.

Kuliah Rangkaian Digital Kuliah 6: Blok Pembangun Logika Kombinasional Teknik Komputer Universitas Gunadarma.

Multiplexers and Demultiplexers, and Encoders and Decoders

1 EE121 John Wakerly Lecture #6 Three-state Outputs Encoders Multiplexers XOR gates.

DLD Lecture 15 Magnitude Comparators and Multiplexers

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Documentation Standards (contd.)

Chapter 33 Basic Logic Gates. 2 Objectives –After completing this chapter, the student should be able to: Identify and explain the function of the basic.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Documentation Standards.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices X-OR gates and Parity circuits Comparators Adders, subtractors,

INTRODUCTION.  Upon completing this topic, you should be able to: Illustrate a basic elements of digital computer system and their functions, Depicts.

1 CS 151: Introduction to Digital Design Chapter 2-10 High Impedance Outputs.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Three-state devices Multiplexers.

CEC 220 Digital Circuit Design Timing Diagrams, MUXs, and Buffers Mon, Oct 5 CEC 220 Digital Circuit Design Slide 1 of 20.

Lecture #18 Page 1 ECE 4110– Sequential Logic Design Lecture #18 Agenda 1.MSI Demultiplexers 2.MSI Tri-State Buffers 3.MSI Comparators Announcements 1.HW.

Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.

Decoders. A decoder is multiple-input, multiple-output logic circuit that converts coded inputs into coded outputs. Input code with fewer bits than the.

Fall 2004EE 3563 Digital Systems Design EE 3563 Encoders  When a device’s output has few bits than the input, it is usually called an “encoder”  It essentially.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Documentation Standards.

Multiplexors Decoders  Decoders are used for forming separate signals for different combination of input signals.  The multiplexer circuit is a digital.

Digital System Design Multiplexers and Demultiplexers, and Encoders and Decoders.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Multiplexers.

ECE 2110: Introduction to Digital Systems Chapter 6 Review.

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices XOR and parity check Circuits.

ECE 3110: Introduction to Digital Systems Chapter 5 Combinational Logic Design Practices Adders,subtractors, ALUs.

Digital Design Jeff Kautzer Univ Wis Milw.

ECE 2110: Introduction to Digital Systems

Multiplexers and Demultiplexers,

Combinational Logic Circuits

ECE 2110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Encoders.

Magnitude Comparator A magnitude comparator is a combinational circuit that compares two numbers, A and B, and then determines their relative magnitudes.

EET107/3 DIGITAL ELECTRONICS 1

Digital System Design Combinational Logic

Arithmetic Circuits.

Presentation transcript:

Three-state devices Multiplexers ECE 3110: Introduction to Digital Systems Chapter 6 Combinational Logic Design Practices Three-state devices Multiplexers

Three State Buffers/Drivers A buffer/inverter with enable input Buffer Buffer Inverter Inverter Active High Enable Active Low Enable Active High Enable Active Low Enable The device behaves like an ordinary buffer/inverter when the enable input is asserted. The output is floating ( High Impedance, Hi-Z ) when the enable input is deasserted ( The input is isolated from the output, behaves as if it did not exist) Application: Controlling the access of a single line/bus by multiple devices

Three-state buffers Output = LOW, HIGH, or Hi-Z. Can tie multiple outputs together, if at most one at a time is driven.

8 sources share a three-state party line

Timing considerations

Standard SSI/MSI 3-state buffers SSI: 74x125, 74x126 (independent enable inputs) MSI: 74x541 and varieties such as 74x540, 74x240, 74x241

Octal non-inverting 3-state buffer Hysteresis

Driver application

Three-state transceiver Pairs of 3-state buffers connected in opposite directions between each pair of pins, so data can be transferred in either direction. DIR determines the direction of transfer (A-->B or B-->A)

Transceiver application Bidirectional buses

Multiplexers (Mux) E.g. Put between Processor’s registers and ALU A 16-bit processor where 3-bit field specifies one of 8 registers. The 3-bit field is connected to the select inputs of an 8-input, 16-bit Mux. Select one of n sources of data to transmit on a bus.

MSI: 74x151 8-input 1-bit multiplexer

74x151 truth table

Other multiplexer varieties 2-input, 4-bit-wide 74x157 4-input, 2-bit-wide 74x153

Expanding Multiplexers 32-to-1 Mux

Demultiplexers A Mux is used to select one of n sources of data to transmit on a bus. A demultiplexer can be used to route the bus data to one of m destinations. Just the inverse of a mux. A binary decoder with an enable input can be used as a Demux. E.g. 74x139 can be used as a 2-bit, 4-output Demux.

Homework #8 (Due: 04/09/2007 ) Notes: On all timing calculation problems, describe the circuit path used and show each number in the calculation. Eg. Twct=T1+T2 T1=TpHL (specify inputs that are causing the transition, i.e. which row. Also show if you picked max or typical Tp values)

Next… XOR gates and Parity circuits Comparators Reading Wakerly CH-6.8-6.9