Variation Aware Application Scheduling in Multi-core Systems Lavanya Subramanian, Aman Kumar Carnegie Mellon University {lsubrama,

Document Map Motivation Motivation Leakage Power and Frequency Variations in CMP Leakage Power and Frequency Variations in CMP Problem Problem Application scheduling exploiting frequency variation and leakage per core in CMPs Application scheduling exploiting frequency variation and leakage per core in CMPs Related Work Related Work Proposed Scheme Proposed Scheme Unified Power Performance Approach Unified Power Performance Approach Milestones Milestones 1

Motivation Variations in chip multi processors are a major concern. There are two components to this: The die-to-die component. The within-die component. At the transistor/device level, these are variations in L eff V th These variations in L eff and V th translate into frequency and leakage current variations at the micro-architecture level. 2

Motivation (contd…) Why a UNIFIED Power/Performance approach?? For cores that can operate at a specific maximum frequency, there is a wide variation in the leakage profiles. Analogously, for cores that have a certain leakage power, there is a wide spread in the maximum frequency characteristics. [3] 3

Problem The perspective of a chip multi processor being a homogenous set of cores is hence not a practical one. A CMP has to be relooked as: a collection of heterogeneous cores each core operating at different frequency each core with a different power profile 4

Related Work Work being done at UIUC, talks about a set of scheduling algorithms taking either power or performance in account but not both together. [1] The basic power efficiency inclined algorithm ( VarP ) tries to map applications onto the least leaky cores. The enhanced version of this ( VarP+AppP ) tries to map the highest dynamic power consuming applications onto the least leaky cores. Similarly, the performance centric algorithms (VarF) map applications onto the fastest cores. 5

Proposed Scheme 1.Rank the cores in the order of the maximum frequencies. 2.Obtain the static leakage power number for each core (profiled statically at a nominal temperature) 3.Rank the applications in the order of dynamic power (obtained by static profiling on a core) 4.For each application, starting from the highest dynamic power one, map the application onto the core with the highest frequency, with the least leakage. This could be achieved by sorting the cores in frequency and leakage bins/levels. 6

Milestones Milestone 1.1: Building variability information into the CMP simulator. Static profiling of applications. Milestone 2: Building a scheduler into the CMP simulator. Milestone 3: Implementing and analyzing the proposed scheme against the baseline algorithms. 7

References [1] R. Teodorescu and J. Torrellas. Variation-aware application scheduling and power management for chip multiprocessors. In ISCA’08: Proceedings of the 35th annual InternationalSymposium on Computer Architecture, 2008 [2] Y. Abulafia and A. Kornfeld. Estimation of FMAX and ISB in microprocessors. IEEE Transactions on VLSI Systems, 13(10), Oct 2006 [3] S. Borkar et. al., “Parameter variations and impact on circuits and micro-architecture,” Proc. DAC 2003, pp

Questions !! 9