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A Low-Power Analog Bus for On-Chip Digital Communication

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1 A Low-Power Analog Bus for On-Chip Digital Communication
8 June 2019 A Low-Power Analog Bus for On-Chip Digital Communication Master’s Thesis Defense Farah Naz Taher Thesis Advisor: Dr. Vishwani D. Agrawal Committee Members: Dr. Victor P. Nelson, Dr. Adit D. Singh June 21, 2013 Farah Naz Taher

2 Outline Motivation Background Problem Statement Concept Result
8 June 2019 Outline Motivation Background Problem Statement Concept Result Future Work Reference 2 Farah Naz Taher June 8, 2019 Farah Naz Taher

3 Motivation Power Testability Area Performance Farah Naz Taher
8 June 2019 Motivation Power Testability Area Performance 3 Farah Naz Taher June 8, 2019 Farah Naz Taher

4 8 June 2019 Motivation Moore’s Law:  Empirical observation that component density and performance of integrated circuits doubles every year G. E. Moore, 1965 S. E. Thompson et. al., Materials Today 2006. 4 Farah Naz Taher June 8, 2019 Farah Naz Taher

5 8 June 2019 Motivation Pollack's Rule: Each technology generation doubles the number of transistor on a chip which enables that performance increase is roughly proportional to square root of increase in complexity. S. Borkar, DAC 2007 5 Farah Naz Taher June 8, 2019 Farah Naz Taher

6 More on-chip Communication
8 June 2019 Motivation More Transistors More Blocks More Cores More on-chip Communication More Power 6 Farah Naz Taher June 8, 2019 Farah Naz Taher

7 Outline Motivation Background Problem Statement Concept Result
8 June 2019 Outline Motivation Background Problem Statement Concept Result Future Work Reference 7 Farah Naz Taher June 8, 2019 Farah Naz Taher

8 8 June 2019 Bus Structure A bus is a collection of signals (wires) that connects one or more IP components for the purpose of data communication. 8 Farah Naz Taher June 8, 2019 Farah Naz Taher

9 Issues With Parallel Bus
8 June 2019 Issues With Parallel Bus Power Dissipation Routing Complexity Area Signal Integrity and Crosstalk Performance 9 Farah Naz Taher June 8, 2019 Farah Naz Taher

10 Dynamic Power For low swing signaling:
8 June 2019 Dynamic Power For low swing signaling: Average dynamic power for a single wire: Weste and Harris, 2010 10 Farah Naz Taher June 8, 2019 Farah Naz Taher

11 8 June 2019 Dynamic Power If there are n-lines in the bus with similar activity, then the total power consumed by such a bus will be n-times of a single bit line Weste and Harris, 2010 11 Farah Naz Taher June 8, 2019 Farah Naz Taher

12 8 June 2019 Dynamic Power Analysis shows that interconnect power can be over 50% of the dynamic power, over 90% of the interconnect power is consumed by only 10% of the interconnections Weste and Harris, 2010 12 Farah Naz Taher June 8, 2019 Farah Naz Taher

13 8 June 2019 The SerDes Option SerDes is a widely used technique for replacing multiple-lines on-chip bus with a single on-chip line to achieve high speed serial communication. In serial bus architecture, n parallel data bits are serialized at the transmitter side. The data transfer takes place at a speed which is n times higher than the data rate of the parallel data. At the receiver side, the data has to be de-serialized to reproduce the n-bit parallel word. A. Kedia et. al., ISCAS N. Hatta et. al. ISPJ 2006 13 Farah Naz Taher June 8, 2019 Farah Naz Taher

14 Disadvantages of SerDes
8 June 2019 Disadvantages of SerDes Increase in the number of transitions n times faster frequency More Power Consumption Encoding scheme needs to be employed to reduce power consumption. Some proposed methods are: Silent: Low energy transmission LOUD: Bit ordering 14 Farah Naz Taher June 8, 2019 Farah Naz Taher

15 Outline Motivation Background Problem Statement Concept Result
8 June 2019 Outline Motivation Background Problem Statement Concept Result Future Work Reference 15 Farah Naz Taher June 8, 2019 Farah Naz Taher

16 8 June 2019 Problem Statement The objective of this work is to develop a low power analog bus for on-chip communication to replace existing parallel digital bus. 16 Farah Naz Taher June 8, 2019 Farah Naz Taher

17 Outline Motivation Background Problem Statement Concept Result
8 June 2019 Outline Motivation Background Problem Statement Concept Result Future Work Reference 17 Farah Naz Taher June 8, 2019 Farah Naz Taher

18 8 June 2019 Analog Bus Replace n wires of an n-bit digital bus carrying data between cores with just one (or few) wire(s) carrying analog signal(s) encoded into 2n levels of voltage Analog bus uses digital-to-analog converter (DAC) drivers and analog-to-digital converter (ADC) receivers. 18 Farah Naz Taher June 8, 2019 Farah Naz Taher

19 Parallel Bus vs. Analog Bus
8 June 2019 Parallel Bus vs. Analog Bus 19 Farah Naz Taher June 8, 2019 Farah Naz Taher

20 Parallel bus vs. Analog Bus
8 June 2019 Parallel bus vs. Analog Bus 20 Farah Naz Taher June 8, 2019 Farah Naz Taher

21 Parallel Bus Digital Data (Volt) Converted Analog Bus (Volt)
8 June 2019 Analog Bus Parallel Bus Digital Data (Volt) 1 Converted Analog Bus (Volt) 1.00 0.067 0.67 0.00 0.933 0.267 0.133 0.600 0.867 0.333 21 Farah Naz Taher June 8, 2019 Farah Naz Taher

22 8 June 2019 Vswing 22 Farah Naz Taher June 8, 2019 Farah Naz Taher

23 Vswing Total number of possible variations
8 June 2019 Vswing Total number of possible variations Total possible voltage swing Average Voltage swing 23 Farah Naz Taher June 8, 2019 Farah Naz Taher

24 Proposition The analog bus can be used in cases where:
8 June 2019 Proposition The analog bus can be used in cases where: i. Power consumed by analog bus architecture < Power consumed by parallel bus ii. The signal can be reproduced without any error The choice of resolution for substituting the number of lines in digital buses with proposed analog bus depends on two criteria. i. Power consumed by the ADC and DAC ii. Noise margin of signal line 24 Farah Naz Taher June 8, 2019 Farah Naz Taher

25 Proposition The analog bus can be used in cases where:
8 June 2019 Proposition The analog bus can be used in cases where: i. Power consumed by analog bus architecture < Power consumed by parallel bus ii. The signal can be reproduced without any error The choice of resolution for substituting the number of lines in digital buses with proposed analog bus depends on two criteria: i. Power consumed by the ADC and DAC ii. Noise margin of signal line 25 Farah Naz Taher June 8, 2019 Farah Naz Taher

26 Proposition Corollary 1: Corollary 2:
8 June 2019 Proposition Corollary 1: Analog bus is effective only if the power consumed by the analog bus architecture is less than the power consumption of the digital bus. Corollary 2: To reproduce the signal in the digital bus without any error, the noise level should be less than half of the resolution of the ADC. 26 Farah Naz Taher June 8, 2019 Farah Naz Taher

27 Proposition Corollary 1: Corollary 2:
8 June 2019 Proposition Corollary 1: Analog bus is effective only if the power consumed by the analog bus architecture is less than the power consumption of the digital bus. Corollary 2: To reproduce the signal in the digital bus without any error, the noise level should be less than half of the resolution of the ADC. 27 Farah Naz Taher June 8, 2019 Farah Naz Taher

28 Advantages Power Saving Farah Naz Taher June 8, 2019
Less Number of wires Lower Capacitance Lower Voltage Swing Power Saving 28 Farah Naz Taher June 8, 2019 Farah Naz Taher

29 Advantages Potential Savings Farah Naz Taher June 8, 2019 29
Power Crosstalk Multiple Drivers/ Buffers Routing Complexity Wire Area 29 Farah Naz Taher June 8, 2019 Farah Naz Taher

30 Outline Motivation Background Problem Statement Concept
8 June 2019 Outline Motivation Background Problem Statement Concept Experimental Result Future Work Reference 30 Farah Naz Taher June 8, 2019 Farah Naz Taher

31 Experimental Setup Farah Naz Taher June 8, 2019 31 8 June 2019
ITRS Interconnect Roadmap 2012 LTspice IV (Version 4.18b) Baker 2008 31 Farah Naz Taher June 8, 2019 Farah Naz Taher

32 Replacement of 4-Line Parallel Bus
8 June 2019 Replacement of 4-Line Parallel Bus 32 Farah Naz Taher June 8, 2019 Farah Naz Taher

33 Replacement of 4-Line Parallel Bus
8 June 2019 Replacement of 4-Line Parallel Bus Digital Data: Bus Input Analog Data: Simulated DAC Output 33 Farah Naz Taher June 8, 2019 Farah Naz Taher

34 Replacement of 4-line Parallel Bus
8 June 2019 Replacement of 4-line Parallel Bus Bus width = 4, Frequency = 1GHz 34 Farah Naz Taher June 8, 2019 Farah Naz Taher

35 Replacement of 4-line Parallel Bus
8 June 2019 Replacement of 4-line Parallel Bus Bus width = 4, Frequency = 1GHz 35 Farah Naz Taher June 8, 2019 Farah Naz Taher

36 Replacement of 4-line Parallel Bus
8 June 2019 Replacement of 4-line Parallel Bus Bus width = 4, Frequency = 500MHz 36 Farah Naz Taher June 8, 2019 Farah Naz Taher

37 Replacement of 4-line Parallel Bus
8 June 2019 Replacement of 4-line Parallel Bus Bus width = 4, Frequency = 500MHz 37 Farah Naz Taher June 8, 2019 Farah Naz Taher

38 Replacement of 8-Line Parallel Bus
8 June 2019 Replacement of 8-Line Parallel Bus 38 Farah Naz Taher June 8, 2019 Farah Naz Taher

39 Replacement of 8-Line Parallel Bus
8 June 2019 Replacement of 8-Line Parallel Bus Digital Data Analog Data 39 Farah Naz Taher June 8, 2019 Farah Naz Taher

40 Replacement of 8-Line Parallel Bus
8 June 2019 Replacement of 8-Line Parallel Bus Bus width = 8, Frequency = 500MHz 40 Farah Naz Taher June 8, 2019 Farah Naz Taher

41 Replacement of 8-Line Parallel Bus
8 June 2019 Replacement of 8-Line Parallel Bus Bus width = 8, Frequency = 500MHz 41 Farah Naz Taher June 8, 2019 Farah Naz Taher

42 Analysis for f = 500MHz Farah Naz Taher June 8, 2019 42 8 June 2019

43 Analysis Bus Width: 4, Frequency: 500MHz, Length = 1mm
8 June 2019 Analysis Bus Width: 4, Frequency: 500MHz, Length = 1mm The average power consumption per mm for the analog bus is around µW. The average power consumption for a 4-bit bus is 219 µW. Bus Width: 8, Frequency: 500MHz, Length = 1mm The average power consumption per mm for the analog bus is around 18.3 µW. The average power consumption for an 8-bit bus is µW. 43 Farah Naz Taher June 8, 2019 Farah Naz Taher

44 8 June 2019 Analysis The power consumption in the parallel bus has an exponential increase with respect to the bus length whereas the power consumption in the analog bus is increasing slowly. SPICE simulation for an ideal case shows that, the ratio of bus power consumed by the proposed analog scheme to a typical parallel digital scheme is given by Panalog/Pdigital = 1/(3n). 44 Farah Naz Taher June 8, 2019 Farah Naz Taher

45 8 June 2019 Analysis The power consumption of the ADC/DAC can be a design challenge for analog bus. ADC/DAC with a power consumption in µW range exists already. Example: ADC (ADS7924 from Texas Instruments): 5.5µW DAC (LTC1591 from Linear technology): 10µW In the 4-Bit and 8-Bit cases we has an available power margin of 200µW and 450µW respectively. The analog bus architecture will be power beneficial even after addition of 15.5µW power consuming elements. 45 Farah Naz Taher June 8, 2019 Farah Naz Taher

46 Outline Motivation Background Problem Statement Concept
8 June 2019 Outline Motivation Background Problem Statement Concept Experimental Result Future Work Reference 46 Farah Naz Taher June 8, 2019 Farah Naz Taher

47 8 June 2019 Future Work This thesis examined the feasibility of the scheme, much work remains to be done Design Suitable Converters Design Encoding Scheme Analyze the Scheme in Digital Testing Fabricate the System on a Chip 47 Farah Naz Taher June 8, 2019 Farah Naz Taher

48 Outline Motivation Background Problem Statement Concept
8 June 2019 Outline Motivation Background Problem Statement Concept Experimental Result Future Work Reference 48 Farah Naz Taher June 8, 2019 Farah Naz Taher

49 Reference Farah Naz Taher June 8, 2019 49 8 June 2019
“14-Bit and 16-Bit Parallel Low Glitch Multiplying DACs with 4-Quadrant Resistors,“ White Paper, Linear Technology Corporation, Feb “2.2V, 12-Bit, 4-Channel, microPOWER Analog-to-Digital converter With I2C Interface,“ White Paper, Texas Instruments Incorporated, Jan “LTspice IV (Version 4.18b)," Linear Technology Corporation, R. J. Baker, CMOS Mixed-signal Circuit Design. John Wiley & Sons, 2008. S. Borkar, “Thousand Core Chips: A Technology Perspective," in Proc. 44th Design Automation Conference, 2007, pp N. Hatta, N. D. Barli, C. Iwama, L. D. Hung, D. Tashiro, S. Sakai, and H. Tanaka, “Bus Serialization for Reducing Power Consumption," ISPJ Trans. Advanced Computing Systems, vol. 47, no. SIG-3, pp , Mar A. Kedia and R. Saleh, “Power Reduction of On-Chip Serial Links," in IEEE International Symp. Circuits and Systems, 2007, pp B. Li, V. D. Agrawal, and B. Zhang, “Mixed-Signal Compression of Digital Test Data.“ Personal Communication, June 2013. G. E. Moore, “Cramming More Components onto Integrated Circuits," Electronics. Vol. 38, no. 8, Apr Semiconductor Industry Association, “International Technology Roadmap for Semiconductors,“ F. N. Taher and V. D. Agrawal, “A Low-Power Analog Bus Approach for On-Chip Digital Communication," 31st IEEE International Conf. Computer Design, Submitted F. N. Taher, S. Sindia, and V. D. Agrawal, “An Analog Bus for Low Power On-Chip Digital Communication," in Work-in-Progress Poster Session, Design Automation Conference, (Austin, Texas), June 2013. 49 Farah Naz Taher June 8, 2019 Farah Naz Taher

50 8 June 2019 Farah Naz Taher June 8, 2019 Farah Naz Taher

51 8 June 2019 Farah Naz Taher June 8, 2019 Farah Naz Taher

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