1 Computer Organization Today: First Hour: Computer Organization –Section 11.3 of Katz’s Textbook –In-class Activity #1 Second Hour: Test Review

2 Note, the BUS is treated just like a register Note, the BUS is treated just like a register Register Transfer Operations Register transfer operations: PC  BUS IR  BUS AC  BUS MBR  BUS ALU Result  BUS BUS  PC BUS  IR BUS  AC BUS  MBR BUS  ALU B BUS  MAR AC  ALU A (hardwired) Single Bus Design

3 More Realistic Datapath Unit Three Bus Design — Supports more parallelism Single bus replaced by three busses: Memory Bus (MBUS) Result Bus (RBUS) Address Bus (ABUS) Memory Bus (MBUS) Result Bus (RBUS) Address Bus (ABUS)

4 We simplified our datapath further by assuming that MBR is inside the memory system itself and MBUS has two branches. Add Memory Every device in this diagram has control signals that must be operated. RBUS AC MBUS AB ALU Memory N bits wide 2 M words MAR S PC IR MBUS Memory Address ABUS

5 Add Control AC AB ALU MAR S PC FSM IR Memory Address Opcode The control unit is a finite state machine (FSM). Instruction Register Every bit of the Instruction Register (IR), every other register’s OE and LOAD signals, every control input and flag output of the ALU, and every memory control signal is either an input or an output of the control unit. (Shown in red) Reality Note #1:The control unit FSM is huge compared to the FSM examples that we’ve seen thus far!! Reality Note #2: The diagram above is extremely simplified compared to a real processor Reality Note #1:The control unit FSM is huge compared to the FSM examples that we’ve seen thus far!! Reality Note #2: The diagram above is extremely simplified compared to a real processor Control Flow Data Flow RBUS MBUS Memory N bits wide 2 M words MBUS ABUS

6 How does it work? (1) 3. Operand Fetch: Move operand address from IR to MAR Initiate a memory read sequence Store Path AC Load Path AB ALU Memory N bits wide 2 M words MAR S PC FSM IR Instruction Path Memory Address Opcode OPCODE OPERAND SPECIFIER Instruction Format Let's trace an instruction: AC  AC + Mem 1. Instruction Fetch: Move PC to MAR Initiate a memory read sequence Move data from memory to IR 2. Instruction Decode: Opcode bits of IR are input to control FSM Rest of IR bits encode the operand address

7 How does it work? (2) Store Path AC Load Path AB ALU Memory N bits wide 2 M words MAR S PC FSM IR Instruction Path Memory Address Opcode OPCODE OPERAND SPECIFIER Instruction Format 4. Instruction Execute: Data available on load path Move data to ALU input Configure ALU to perform ADD operation Move result S to AC 5. Housekeeping: Update PC to point at next instruction Let us trace an instruction: AC  AC + Mem

8 The Control Unit What the Control unit is doing: Transfers data from one register to another Asserts appropriate control signals We can think about the control unit most easily in terms of a series of register transfers, using a programming-like notation Register transfer notation - A way to represent the detailed implementation of register transfer operations

9 Register to Register moves Register Transfer Notation Instruction fetch: PC  MAR;-- move PC to MAR Memory Read;-- assert Memory READ signal Memory  IR;-- load IR from Memory Instruction Decode:IF IR = ADD_FROM_MEMORY THEN Instruction Execution: Memory  ALU B;-- gate Memory to ALU B AC  ALU A;-- gate AC to ALU A ALU ADD;-- instruct ALU to perform ADD ALU S  AC;-- gate ALU result to AC Assert Control Signal Assert Control Signal Operand fetch: IR  MAR;-- move operand addr to MAR Memory Read;-- assert Memory READ signal Housekeeping: PC+1  PC;-- increment PC

10 Micro-Operations Instruction fetch: PC  ABUS; ABUS  MAR; 1  Read/Write*; MBR  MBUS; MBUS  IR; Instruction Decode:IF IR = LOAD_FROM_MEMORY THEN Instruction Execution: MBR  MBUS; MBUS  ALU B; ALU PASS B; ALU Result  RBUS; RBUS  AC; Operand fetch: IR  MAR; 1  Read/Write*; Housekeeping: PC+1  PC; Instruction Fetch

11 Micro-operations One register transfer operation may be several micro-operations Some operations are directly implemented by functional units: e.g., ADD, Pass B, 0  PC, PC + 1  PC Some others require multiple control operations: e.g., PC  MAR implemented as PC  ABUS and ABUS  MAR

12 Do Activity #1 Now AC AB ALU MAR S PC FSM IR Memory Address Opcode Control Flow Data Flow RBUS MBUS Memory N bits wide 2 M words MBUS ABUS

13 RETAIN THE LAST PAGE(S) (#3 onwards)!! For Next Class: Bring Huang 68HC11 Textbook Required Reading: – Chap 1 of the Huang 68HC11 book This reading is necessary for getting points in the Studio Activity!