Logic and Computer Design Dr. Sanjay P. Ahuja, Ph.D. FIS Distinguished Professor of CIS ( ) School of Computing, UNF

Logic Gates

Registers and Counters A register is a set of flips-flops (ffs) with each ff capable of storing one bit of information. An n-bit register is built from n-ffs and stores n-bits of data.

4-bit Register with Parallel Load having clock skew due to clock gating

4-bit Register with Parallel Load

Shift Register

Shift Register with Parallel Load

Bidirectional Shift Register with Parallel Load

Ripple and Synchronous Counters

4-Bit Ripple Counter

4-Bit Binary Ripple Counter with T-FFs

Memory and Programmable Logic Devices Memory is a collection of binary storage cells together with associated circuits needed to transfer information into and out of the cells. Two memory types: 1. RAM Supports read and write operations Volatile 2. ROM Supports only read operations Non-volatile A PLD is an integrated circuit (IC) with internal logic gates/connections that can be changed in some way by a programming process. E.g. having fuses. A PLD may have 100s to millions of gates.

Programmable Logic Devices (PLD) A PLD is an integrated circuit (IC) with internal logic gates/connections that can be changed in some way by a programming process (e.g. having fuses). A PLD may have 100’s to millions of gates.

Block Diagram of Memory Binary information is stored in groups of bits called words. 8-bit word is a byte; 16-bit word has 2 bytes; 32-bit word has 4-bytes Each word is assigned an address. Addresses range from 0 to 2 k -1 where k is the number of address lines.

Memory: Write and Read Operations Steps for Write: 1. Apply binary address of desired word to the address lines. 2. Apply the data bits that must be stored in memory to the data input lines. 3. Activate the Write input. Steps for Read: 1. Apply binary address of desired word to the address lines. 2. Activate the Read input. Memory is made up of RAM ICs plus additional logic circuits. Most RAM ICs have two control inputs: 1. A Chip Select (CS) that selects the chip to be read from/written to. 2. A Read/Write to determine the particular operation.

Memory: Access Time and Write Cycle Time Access Time of a memory read operation is the maximum time from the application of the address to the appearance of the data at the data output lines. Write Cycle Time is the maximum time from the application of the address to the completion of all internal memory operations required to store a word. The number of clock pulses required for a memory request is the integer value greater than or equal to the maximum of the access time and the write cycle time, divided by the clock period. Number of clock pulses = maximum (access time, write cycle time) cycle period Example: For a CPU clock frequency of 50 MHz, the period = 1 / 50 x 10 6 = 20 nseconds For a memory access time = 65 nseconds and memory write cycle time = 75 nseconds, maximum (75, 65) = nseconds = 4 clock pulses devoted to each memory request. 20 nseconds

Memory: SRAM vs DRAM RAM ICs can be either static or dynamic. SRAM consists of internal flip-flops that store the binary information. The stored information remains valid as long as power is applied to the RAM. DRAM stores binary information in the form of electric charges on capacitors. The stored charge tends to discharge with time, and the capacitors must be periodically recharged by refreshing the DRAM. Advantages of DRAM: 1. Reduced power consumption 2. Larger storage capacity in a single memory chip (roughly 3 times of SRAM), 3. Cheaper (less than 1/3 rd of cost/bit of SRAM) 4. Used in main memory Advantages of SRAM: 1. Has shorter read/write cycles, i.e. is faster 2. No refresh required for SRAM 3. Used in cache memory 4. Easier to user

Memory: RAM ICs Internally a RAM chip of m words and n bits/word has an array of mn binary storage cells and circuitry. The circuitry is made of decoders to select the word, read circuits, write circuits and output logic.

Static RAM Cell

Array of RAM ICs

PLDs

ROM (size 32 x 8): has 5:32 decoder and 8 OR gates Each OR gate has 32 programmable connections and there are 8 OR gates for a total of 32 x 8 = 256 programmable connections (fuses). In general, a 2 k x n ROM has a k:2 k decoder and n OR gates each with 2 k inputs connected via fuses to the 2 k outputs of the decoder.

Programmable Logic Array (PLA) F1 = AB + AC + ABC F2 = AC + BC

PLA Implement the following two Boolean functions with a PLA. F1 (A,B,C) = ∑m (0, 1, 2, 4) F2 (A,B,C) = ∑m (0, 5, 6, 7)

Programmable Array Logic (PAL)