1 Metal-Oxide-Semicondutor FET (MOSFET)

Copyright  2004 by Oxford University Press, Inc. 2 Figure 4.1 Physical structure of the enhancement-type NMOS transistor: (a) perspective view; (b) cross-section. Typically L = 0.1 to 3  m, W = 0.2 to 100  m, and the thickness of the oxide layer (t ox ) is in the range of 2 to 50 nm.

Copyright  2004 by Oxford University Press, Inc. 3 Figure 4.2 The enhancement-type NMOS transistor with a positive voltage applied to the gate. An n channel is induced at the top of the substrate beneath the gate.

SJTU J. Chen 4 Device structure of MOSFET (n-type) p-type Semiconductor Substrate (Body) Body(B) n+n+ n+n+ Oxide (SiO 2 ) Source(S) Gate(G) Drain(D) Metal For normal operation, it is needed to create a conducting channel between Source and Drain Channel area

SJTU J. Chen 5  An n channel can be induced at the top of the substrate beneath the gate by applying a positive voltage to the gate  The channel is an inversion layerinversion layer  The value of V GS at which a sufficient number of mobile electrons accumulate to form a conducting channel is called the threshold voltage (V t ) Creating a channel for current flow

SJTU J. Chen 6  L = 0.1 to 3  m  W = 0.2 to 100  m  T ox = 2 to 50 nm Device structure of MOSFET (n-type) Cross-section view

Copyright  2004 by Oxford University Press, Inc. 7 Figure 4.3 An NMOS transistor with v GS > V t and with a small v DS applied. The device acts as a resistance whose value is determined by v GS. Specifically, the channel conductance is proportional to v GS – V t’ and thus i D is proportional to ( v GS – V t ) v DS. Note that the depletion region is not shown (for simplicity).

Copyright  2004 by Oxford University Press, Inc. 8 Figure 4.5 Operation of the enhancement NMOS transistor as v DS is increased. The induced channel acquires a tapered shape, and its resistance increases as v DS is increased. Here, v GS is kept constant at a value > V t.

Copyright  2004 by Oxford University Press, Inc. 9 Figure 4.4 The i D – v DS characteristics of the MOSFET in Fig. 4.3 when the voltage applied between drain and source, v DS, is kept small. The device operates as a linear resistor whose value is controlled by v GS.

Copyright  2004 by Oxford University Press, Inc. 10 Figure 4.6 The drain current i D versus the drain-to-source voltage v DS for an enhancement-type NMOS transistor operated with v GS > V t.

Copyright  2004 by Oxford University Press, Inc. 11 Figure 4.9 Cross-section of a CMOS integrated circuit. Note that the PMOS transistor is formed in a separate n-type region, known as an n well. Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well. Not shown are the connections made to the p-type body and to the n well; the latter functions as the body terminal for the p-channel device.

Copyright  2004 by Oxford University Press, Inc SJTU J. Chen 12  The PMOS transistor is formed in n well.  Another arrangement is also possible in which an n-type body is used and the n device is formed in a p well.  CMOS is the most widely used of all the analog and digital IC circuits. Complementary MOS or CMOS

Copyright  2004 by Oxford University Press, Inc. Figure: n-Channel JFET. The Junction Field Effect Transistor (JFET)

Copyright  2004 by Oxford University Press, Inc. Figure: n-Channel JFET and Biasing Circuit. Biasing the JFET

Copyright  2004 by Oxford University Press, Inc. Figure: The nonconductive depletion region becomes broader with increased reverse bias. (Note: The two gate regions of each FET are connected to each other.) Operation of JFET at Various Gate Bias Potentials

Copyright  2004 by Oxford University Press, Inc. PP + - DC Voltage Source N N Operation of a JFET Gate Drain Source

Copyright  2004 by Oxford University Press, Inc. Figure: Circuit for drain characteristics of the n-channel JFET and its Drain characteristics. Characteristics of n-JFET

Copyright  2004 by Oxford University Press, Inc. Figure: n-Channel FET for v GS = 0. n-Channel JFET

19N - c h a n n e l Depletion layer G D S GDS n-type Semiconductor Junction FET P+P+P+P+ P+P+P+P+

20 U GS = 0 U GS < 0 U GS = U GS(off) D S P+P+P+P+ Physical operation under v DS =0 G P+P+P+P+DS P+P+P+P+ G P+P+P+P+ DS G P+P+P+P+ P+P+P+P+

21 The effect of U DS on I D for U GS(off) <U GS < 0