ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Design Metrics ECE442: Digital Electronics

CSUN, Spring-2010, Zahid Overview  Digital integrated circuits experience exponential growth in complexity (Moore’s law) and performance  Design in the deep submicron (DSM) era creates new challenges l Devices become somewhat different l Global clocking becomes more challenging l Interconnect effects play a more significant role l Power dissipation may be the limiting factor  Our goal in this class will be to understand and design digital integrated circuits in advanced technologies  Today we look at some basic design metrics

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Fundamental Design Metrics  Functionality  Cost l NRE (fixed) costs - design effort l RE (variable) costs - cost of parts, assembly, test  Reliability, robustness l Noise margins l Noise immunity  Performance l Speed (delay) l Power consumption; energy  Time-to-market

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Cost of Integrated Circuits  NRE (non-recurring engineering) costs l Fixed cost to produce the design -design effort -design verification effort -mask generation l Influenced by the design complexity and designer productivity l More pronounced for small volume products  Recurring costs – proportional to product volume l silicon processing -also proportional to chip area l assembly (packaging) l test fixed cost cost per IC = variable cost per IC volume

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid NRE Cost is Increasing

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Silicon Wafer Single die Wafer From

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Recurring Costs cost of die + cost of die test + cost of packaging variable cost = final test yield cost of wafer cost of die = dies per wafer × die yield  × (wafer diameter/2) 2  × wafer diameter dies per wafer =  die area  2 × die area die yield = (1 + (defects per unit area × die area)/  ) - 

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Yield Example  Example l wafer size of 12 inches, die size of 2.5 cm 2, 1 defects/cm 2,  = 3 (measure of manufacturing process complexity) l 252 dies/wafer (remember, wafers round & dies square) l die yield of 16% l 252 x 16% = only 40 dies/wafer die yield !  Die cost is strong function of die area proportional to the third or fourth power of the die area

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Examples of Cost Metrics (circa 1994) ChipMetal layers Line width Wafer cost Defects /cm 2 Area (mm 2 ) Dies/ wafer YieldDie cost 386DX20.90$ %$4 486DX230.80$ %$12 PowerPC $ %$53 HP PA $ %$73 DEC Alpha 30.70$ %$149 Super SPARC 30.70$ %$272 Pentium30.80$ %$417

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Reliability: Noise in Digital Integrated Circuits  Noise – unwanted variations of voltages and currents at the logic nodes V DD v(t) i(t)  From two wires placed side by side l capacitive coupling -voltage change on one wire can influence signal on the neighboring wire -cross talk l inductive coupling -current change on one wire can influence signal on the neighboring wire  From noise on the power and ground supply rails l can influence signal levels in the gate

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Example of Capacitive Coupling  Signal wire glitches as large as 80% of the supply voltage will be common due to crosstalk between neighboring wires as feature sizes continue to scale Crosstalk vs. Technology 160nm CMOS 120nm CMOS 350nm CMOS 250nm CMOS Pulsed Signal Black line quiet Red lines pulsed Glitches strength vs technology From Dunlop, Lucent, 2000

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Static Gate Behavior  Steady-state parameters of a gate – static behavior – tell how robust a circuit is with respect to both variations in the manufacturing process and to noise disturbances.  Digital circuits perform operations on Boolean variables x  {0,1}  A logical variable is associated with a nominal voltage level for each logic state 1  V OH and 0  V OL  Difference between V OH and V OL is the logic or signal swing V sw V(y)V(x) V OH = ! (V OL ) V OL = ! (V OH )

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid DC Operation : Voltage Transfer Characteristics(VTC) V(x) V(y) f V(x)  Plot of output voltage as a function of the input voltage V OH = f (V IL ) V OL V OH V(y)=V(x) Switching Threshold VMVM V OL = f (V IH )

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Mapping Logic Levels to the Voltage Domain V(x) V(y) Slope = -1 V OH V OL V IL V IH "1" "0" Undefined Region V OH V OL V IL V IH  The regions of acceptable high and low voltages are delimited by V IH and V IL that represent the points on the VTC curve where the gain = -1

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Noise Margins Undefined Region "1" "0" Gate Output Gate Input V OH V IL V OL V IH Noise Margin High Noise Margin Low NM H = V OH - V IH NM L = V IL - V OL Gnd V DD Gnd  For robust circuits, want the “0” and “1” intervals to be a s large as possible  Large noise margins are desirable, but not sufficient …

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid The Regenerative Property v0v0 v1v1 v2v2 v3v3 v4v4 v5v5 v6v6 v0v0 v2v2 v1v1  A gate with regenerative property ensure that a disturbed signal converges back to a nominal voltage level

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Conditions for Regeneration v 1 = f(v 0 )  v 1 = finv(v 2 ) v0v0 v1v1 v2v2 v3v3 v4v4 v5v5 v6v6 v0v0 v1v1 v2v2 v3v3 f(v) finv(v) Regenerative Gate v0v0 v1v1 v2v2 v3v3 f(v) finv(v) Non-regenerative Gate  To be regenerative, the VTC must have a transient region with a gain greater than 1 (in absolute value) bordered by two valid zones where the gain is smaller than 1. Such a gate has two stable operating points.

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Noise Immunity  Noise immunity expresses the ability of the system to process and transmit information correctly in the presence of noise  For good noise immunity, the signal swing (i.e., the difference between V OH and V OL ) and the noise margin have to be large enough to overpower the impact of fixed sources of noise  Noise margin expresses the ability of a circuit to overpower a noise source l noise sources: supply noise, cross talk, interference, offset  Absolute noise margin values are deceptive l a floating node is more easily disturbed than a node driven by a low impedance (in terms of voltage)

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Directivity  A gate must be unidirectional: changes in an output level should not appear at any unchanging input of the same circuit l In real circuits full directivity is an illusion (e.g., due to capacitive coupling between inputs and outputs)  Key metrics: output impedance of the driver and input impedance of the receiver l ideally, the output impedance of the driver should be zero and l input impedance of the receiver should be infinity

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Fan-In and Fan-Out  Fan-out – number of load gates connected to the output of the driving gate l gates with large fan-out are slower N M  Fan-in – the number of inputs to the gate l gates with large fan-in are bigger and slower

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid The Ideal Inverter  The ideal gate should have l infinite gain in the transition region l a gate threshold located in the middle of the logic swing l high and low noise margins equal to half the swing l input and output impedances of infinity and zero, respectively. g = -  V out V in R i =  R o = 0 Fan-out =  NM H = NM L = VDD/2

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Delay Definitions t V out V in input waveform output waveform t p = (t pHL + t pLH )/2 Propagation delay t 50% t pHL 50% t pLH tftf 90% 10% trtr signal slopes V in V out

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Modeling Propagation Delay  Model circuit as first-order RC network R C v in v out v out (t) = (1 – e –t/  )V where  = RC Time to reach 50% point is t = ln(2)  = 0.69  Time to reach 90% point is t = ln(9)  = 2.2   Matches the delay of an inverter gate

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Power and Energy Dissipation  Power consumption: how much energy is consumed per operation and how much heat the circuit dissipates l supply line sizing (determined by peak power) P peak = V dd i peak l battery lifetime (determined by average power dissipation) p(t) = v(t)i(t) = V dd i(t) P avg = 1/T  p(t) dt = V dd /T  i dd (t) dt l packaging and cooling requirements  Two important components: static and dynamic Dynamic Power is defined as P (watts) = f C L V dd 2 where f is the switching frequency and C L is the “load capacitor”

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid Power and Energy Dissipation  Propagation delay and the power consumption of a gate are related  Propagation delay is (mostly) determined by the speed at which a given amount of energy can be stored on the gate capacitors l the faster the energy transfer (higher power dissipation) the faster the gate  For a given technology and gate topology, the product of the power consumption and the propagation delay is a constant l Power-delay product (PDP) – energy consumed by the gate per switching event  An ideal gate is one that is fast and consumes little energy, so the ultimate quality metric is l Energy-delay product (EDP) = power-delay 2

ECE442: Digital ElectronicsCSUN, Spring-2010, Zahid  Digital integrated circuits have come a long way and still have quite some potential left for the coming decades  Some interesting challenges ahead l Getting a clear perspective on the challenges and potential solutions is the purpose of this course  Understanding the design metrics that govern digital design is crucial l Cost, reliability, speed, power and energy dissipation Summary