RapidIO Overview October 2002. © Copyright 2002 RapidIOTrade Association RapidIO Steering and Sponsoring Member Companies.

Slides:

Advertisements

Similar presentations

Flexible I/O in a Rigid World

Advertisements

Nios Multi Processor Ethernet Embedded Platform Final Presentation

Architectural Freedom with Serial Interconnects NDIA Conference San Diego, CA October 20-23, 2003 Emmanuel Eriksson – Dy 4 Systems

Digital RF Stabilization System Based on MicroTCA Technology - Libera LLRF Robert Černe May 2010, RT10, Lisboa

#147 MAPLD 2005Mark A. Johnson1 Design of a Reusable SpaceWire Link Interface for Space Avionics and Instrumentation Mark A. Johnson Senior Research Engineer.

I/O Channels I/O devices getting more sophisticated e.g. 3D graphics cards CPU instructs I/O controller to do transfer I/O controller does entire transfer.

t Popularity of the Internet t Provides universal interconnection between individual groups that use different hardware suited for their needs t Based.

1 Chapter 14 Embedded Processing Cores. 2 Overview RISC: Reduced Instruction Set Computer RISC-based processor: PowerPC, ARM and MIPS The embedded processor.

6/30/2015HY220: Ιάκωβος Μαυροειδής1 Moore’s Law Gordon Moore (co-founder of Intel) predicted in 1965 that the transistor density of semiconductor chips.

Protocols and the TCP/IP Suite Asynchronous Transfer Mode (ATM)

Chapter 2 Protocols and the TCP/IP Suite 1 Chapter 5 Asynchronous Transfer Mode (ATM)

Development of an ATCA IPMI Controller Mezzanine Board to be used in the ATCA developments for the ATLAS Liquid Argon upgrade Nicolas Dumont Dayot, LAPP.

Router Architectures An overview of router architectures.

USB 2.0 to SD-Card File Transfer

© Wiley Inc All Rights Reserved. CCNA: Cisco Certified Network Associate Study Guide CHAPTER 1: Internetworking.

Router Architectures An overview of router architectures.

Getting Started With DSP A. What is DSP? B. Which TI DSP do I use? Highest performance C6000 Most power efficient C5000 Control optimized C2000 TMS320C6000™

Interconnection Protocol Mustafa Kara Term Work.

C OLUMBIA U NIVERSITY Lightwave Research Laboratory Embedding Real-Time Substrate Measurements for Cross-Layer Communications Caroline Lai, Franz Fidler,

Advantages of Reconfigurable System Architectures

EKT303/4 PRINCIPLES OF PRINCIPLES OF COMPUTER ARCHITECTURE (PoCA)

RSC Williams MAPLD 2005/BOF-S1 A Linux-based Software Environment for the Reconfigurable Scalable Computing Project John A. Williams 1

Keith Williamson Manager Technical Marketing

How to construct world-class VoIP applications on next generation hardware David Duffett, Aculab.

IDT Powering What’s Next in Communications 01 May 2000.

“ Analyzer for 40Gbit Ethernet “ (Bi-semestrial project) Executers: פריד מחאג ' נה Farid Mahajna Husam Kadan חוסאם קעדאן Instructor:

The University of New Hampshire InterOperability Laboratory Introduction To PCIe Express © 2011 University of New Hampshire.

Silicon Building Blocks for Blade Server Designs accelerate your Innovation.

11 Workshop on Information Technology March Shanghaï CONFIDENTIAL Architectures & Digital IC design.

InfiniSwitch Company Confidential. 2 InfiniSwitch Agenda InfiniBand Overview Company Overview Product Strategy Q&A.

SLAC Particle Physics & Astrophysics The Cluster Interconnect Module (CIM) – Networking RCEs RCE Training Workshop Matt Weaver,

Lect1..ppt - 01/06/05 CDA 6505 Network Architecture and Client/Server Computing Lecture 5 Asynchronous Transfer Mode (ATM) by Zornitza Genova Prodanoff.

Universal Reconfigurable Processing Platform for Space Presented by Dorian Seagrave Gordonicus LLC.

Introduction to Network Basic 1. Agenda – - Internetworking Basic – - OSI Layer – - TCP/IP Model – - IP Addressing – - Subnetting & VLSM – - The Internal.

EEC4113 Data Communication & Multimedia System Chapter 1: Introduction by Muhazam Mustapha, September 2011.

VPX Cover Overview and Update “VPX, Open VPX, and VPX REDI ” are trademarks of VITA.

Page 1 Reconfigurable Communications Processor Principal Investigator: Chris Papachristou Task Number: NAG Electrical Engineering & Computer Science.

Agenda 1. QUIZ 2. TEST & LAST WEEK’S QUIZ 3. HOMEWORK 4. SWITCHING 5. POINT-TO-POINT PROTOCOL 6. INTEGRATED SERVICES DIGITAL NETWORK (ISDN) 7. X.25 8.

March 9, 2015 San Jose Compute Engineering Workshop.

What is Bandwidth on Demand ? Bandwidth on Demand (BoD) is based on a technology that employs a new way of managing and controlling SONET-based equipment.

Cisco Discovery Protocol. CDP and Router Boot Up When a Cisco device boots up, CDP starts up automatically and allows the device to detect neighbor devices.

Infiniband Bart Taylor. What it is InfiniBand™ Architecture defines a new interconnect technology for servers that changes the way data centers will be.

MAPLD 2005/254C. Papachristou 1 Reconfigurable and Evolvable Hardware Fabric Chris Papachristou, Frank Wolff Robert Ewing Electrical Engineering & Computer.

CS 4396 Computer Networks Lab Router Architectures.

Axel Jantsch 1 Networks on Chip Axel Jantsch 1 Shashi Kumar 1, Juha-Pekka Soininen 2, Martti Forsell 2, Mikael Millberg 1, Johnny Öberg 1, Kari Tiensurjä.

Page 1 Industrial Technology Research Institute Computer & Communication Research Laboratories Network Processor +Programmable semiconductor devices for.

Designing Applications Using DSP Modules

Computer Networks Syed Md. Ashraful Karim Lecturer, CSE BU.

Interconnection network network interface and a case study.

Slide title In CAPITALS 50 pt Slide subtitle 32 pt Protection concerns using Switched Ethernet as internal bus for a Telecommunication Network Element.

Intro to Distributed Systems and Networks Hank Levy.

Local-Area Networks. Topology Defines the Structure of the Network – Physical topology – actual layout of the wire (media) – Logical topology – defines.

OSI ARCHITECTURE IN OSI, ACTUAL INFORMATION IS OVERHEADED BY PROTOCOL LAYERS IF ALL SEVEN LAYERS ARE OVERHEADED, THEN AS LITTLE AS 15% OF THE TRANSMITTED.

RapidIO based Low Latency Heterogeneous Supercomputing Devashish Paul, Director Strategic Marketing, Systems Solutions

Univ. of TehranIntroduction to Computer Network1 An Introduction to Computer Networks University of Tehran Dept. of EE and Computer Engineering By: Dr.

IETF CAPWAP Protocol Objectives China Mobile,Huawei Technology, Intel Corporation,ZTE,RITT Nov. 8,2004.

Rohde & Schwarz Topex TOPEX IP Radio Gateway July 2011.

Firmware and Software for the PPM DU S. Anvar, H. Le Provost, Y.Moudden, F. Louis, E.Zonca – CEA Saclay IRFU – Amsterdam/NIKHEF, 2011 March 30.

Real-Time Systems Lab. OSGi overview January 23, 2002 Sung-ho Park.

Data and Computer Communications Eighth Edition by William Stallings Chapter 1 – Data Communications, Data Networks, and the Internet.

Computer Networks Laboratory project. In cooperation with Mellanox Technologies Ltd. Guided by: Crupnicoff Diego. Gurewitz Omer. Students: Cohen Erez.

QM/BUPT Joint Programme

Flexible I/O in a Rigid World

Distributed Systems.

OCP: High Performance Computing Project

Cisco 7200 Multiservice Solutions

Low Latency Analytics HPC Clusters

Chapter 3: Open Systems Interconnection (OSI) Model

Network-on-Chip Programmable Platform in Versal™ ACAP Architecture

EEC4113 Data Communication & Multimedia System Chapter 1: Introduction by Muhazam Mustapha, July 2010.

Presentation transcript:

RapidIO Overview October 2002

© Copyright 2002 RapidIOTrade Association RapidIO Steering and Sponsoring Member Companies

© Copyright 2002 RapidIOTrade Association Member Company Categories System Logic & IP Cadence Cypress Semi Emulex Hifn IC4IC Ltd. Leopard Logic LSI Logic Marvell Mindstream National Semi RedSwitch PLX PMC Sierra Silicon Logic Eng Stargen Tundra CPUs, DSPs, NPUs Analog Devices IBM IDT Intel Intrinsity Motorola Texas Instruments Test Equipment Agilent Tektronix Teradyne System OEMs Alcatel Cisco Systems DY4/Force EMC Ericsson Huawei Technologies Lucent Mercury Computer Nokia Raytheon Rydal Research SKY Computer Spectrum Signal Processing Systran Tek Microsystems Thales Computers Vivace Networks VMETRO FPGA Actel Altera Xilinx Quicklogic Software MontaVista OSE Systems QNX WindRiver Design Tools Cadence Synopsys

© Copyright 2002 RapidIOTrade Association What is RapidIO? Packet-based memory-mapped switched interconnect architecture for in-system communications –Also supports device-level messaging –Also supports cc-NUMA (Globally Shared Memory) –LVDS Parallel interface for processors –SerDes Serial interface for DSP, Serial Backplane applications –High reliability –Open Standard

© Copyright 2002 RapidIOTrade Association Common Networking Topology Line Card DSP RapidIO ASIC RapidIO ASIC MEM Ethernet / IP ATM / SONET Infiniband / Fibrechannel TDM Voice Traffic Physical Layer Interface Physical Layer Interface Data Serial RapidIO Data Path Fabric RapidIO Fabric Control Plane Traffic Aggregation Traffic Aggregation NPU Host uP Host uP Control DSP Host Card MEMy Host uP MEM Host uP RapidIO Fabric RapidIO Fabric Ethernet

© Copyright 2002 RapidIOTrade Association Supported Application Classes Processor Local Bus Processor Clustering –Coherent and Non-Coherent DSP Farm Serial Backplane These applications are supported by the current specs

© Copyright 2002 RapidIOTrade Association Protocol Enhancements Virtual Channels Packet/Cell Encapsulation Flow Control Multicast Relaxed Acknowledgement Rules Possible enhancements to RapidIO that are currently under consideration These enhancements are designed to make RapidIO more suitable as a data- plane technology for embedded systems

© Copyright 2002 RapidIOTrade Association Supporting Technologies/Standards System Bringup APIs –Software APIs for booting and configuring systems HIP Platform Specification –Hardware interoperability evaluation board Error Management Specification –Hardware and Software specs for the handling of errors detected by RapidIO in a system

© Copyright 2002 RapidIOTrade Association Mechanical Standards Mezzanine Card –Work going on the extend PMC card standard to support RapidIO RapidIO on cPCI 2.x –Taskgroup working to produce standard for mapping of Serial RapidIO in CompactPCI 2.x chassis