Infrastructure design & implementation of MIPS processors for students lab based on Bluespec HDL Students: Danny Hofshi, Shai Shachrur Supervisor: Mony Orbach Winter 2012

Lab Vision - The student performing the lab will understand a MIPS processor, - The student will have the tools for performance analyzing of a particular MIPS. - He will implement & evaluate different types of architecture improvements. - He will sense the advantages of various improvements without being concerned with the technical aspects of handling the experiment setup.

FPGA Bluespec Scemi Bluespec HDL C++

Assumptions The students attending the lab are already familiar with basic aspects of logic design & MIPS architecture. The students will receive complementary knowledge relevant for the experiment.

staff Academic supervisor: Yoav Etsion. Project supervisor: Mony Orbach. Project coordinator: Eli Shushan. Application engineering: Inna Rivkin.

Abstract The lab we aspire to create is in respect to a course performed by Dr Derek Chiou from the university of Texas at the recent summer semester. Using new features of the Bluespec HDL and its environment we are able to create a lab setup that enables the student to easily understand & experience processors architecture and performances. The Hardware and software will be described in details in the next slides.

Work Flow

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions & Program for testing Running a pilot group Danny & Shai Lab staff

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions & Program for testing Running a pilot group Danny & Shai Lab staff Part A Part B

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions & Program for testing Running a pilot group Danny & Shai Lab staff

The basic MIPS architecture The purpose of the below MIPS is to use as a basis for improvements during the experiment. The improvements will be: Pipelining, Branch prediction & Cache the MIPS will be multi cycle.(3-4 cycles) Instruction & data memory will be multi cycle. When instruction is not available, the processor will be in idle. When performing load word operation from the data memory the processor will be in idle until data is retrieved. The system will have Ability to control the clock frequency. MIPS Performance counter will be linked to a C++ environment.

MIPS Components Xilinx BRAM (Verilog) BSV Wrapper Xilinx BRAM (Verilog) BSV Wrapper BlueSpec S C E M I - PCIe -Clk control Communicating with a c++ environment using generic interface BlueSpec

Part A Part B Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions Program for testing Running a pilot group Danny & Shai Lab staff

Performance questions What are the performances we would like to capture ? What is the structure and what are the units we would like to display the performance details with ? Which program to run for the above performance analyzing ? Will it be a single program or several programs ? …

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions Program for testing Running a pilot group Danny & Shai Lab staff Part A Part B

Test sync & conclusions Running the test program. Checking the performance counters. Modifying the simulation environment appereance.

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions Program for testing Running a pilot group Danny & Shai Lab staff Part A Part B

MIPS improvements Pipeline. Cache. Branch prediction. Discussion: How we would like the students to implement the improvements ? - Will he get a ready made Bit streams ? - Will he get a partial implemented code and will complete the code by himself ?

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions Program for testing Running a pilot group Danny & Shai Lab staff Part A Part B

Experiment flow A-Z experiment booklet. Preparation report. complementary knowledge references. Video ? (By Derek Chiou)

Project Characterization Multi cycle MIPS hardware Adjusting the experiment flow Test, Sync & Conclusions Designing the MIPS improvements performance questions Program for testing Running a pilot group Danny & Shai Lab staff Part A Part B

Pilot group We implement Meow prediction ?

Focus on us Shai & Danny

Project Goals Part A: Creating the Laboratory working environment. 1. Hardware environment – RTL, interface to outer world ( pci - express ), Xilinx utilities. 2. Software environment – simulation of a MIPS processor on the above RTL using simplified commands, the same environment will be used for emulation and simulation. Part B: Designing 3 different MIPS improvements which will work on the same environment, DFT, performance counters. We will implement In separate: 1. Pipeline 2. Branch prediction. 3. Cash

Hardware environment The MIPS Processor will be implemented on a Xilinx Virtex-5 FPGA development board. DUT integration with a PC will be implemented using a PCIe bus. untimed TB vs. cycle accurate DUT. Bit stream loading through a Jtag connection. Lab students will run the experiment on a Linux O.S using executable SCEMI commands ( supported by Bluespec environment).

Hardware PCIe cable Virtex 5 FPGA Linux Environment

Software environment Simulation: Simple “Build” scripts will execute a complete simulation flow. (compile, link, burn, code loader, simulate, results view) TCP protocol replaces PCIe bus in simulation. simulation & emulation will have the same structure & units of results for all the tested processors.

Software environment At the background: The MIPS processor will be written using BlueSpec HDL. Memory blocks using Xilinx native BRAM Bluespec modules. SCEMI: a generic protocol will connect between a C++ simulation environment to the DUT. Ability to access MIPS Imemory and Dmemory (R/W) from the PC environment. NOTE: BlueSpec & PlanAhead (Xilinx compiler) versions need to be pre determined. Any changes in the compilers versions will probably cause problems.

Declarations We set software versions to be: PlanAhed Version 14.1, BlueSpec D redhat Linux running tcsh shell

Discussion

Gantt Chart Part-A Mar Feb- Mar Feb Jan- Feb Jan Finalizing Characteristic Presentation Part A submission Simulating the MIPS on a real- time environment using SCEMI and a test code. Integrating the memory with the MIPS processor & creating a C++ Test Bench. Creating and simulating Memory wrappers (I-memory and D- memory) Creating a SCEMI top for the MIPS processor (Including a program loader) Done preparing a dedicated server for A PCIe connection Running a Simple SCEMI environment from C++ to FPGA GCD Testing & conclusions Part-A Staff period to prepare the first part – Program for testing & data inquiry from the MIPS PNR Part -B